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Standard PCS in Low Latency Conguration.......................................................................................... 5-6
Low Latency Custom Conguration Channel Options.............................................................. 5-7
Document Revision History.....................................................................................................................5-10
Transceiver Loopback Support........................................................................... 6-1
Serial Loopback............................................................................................................................................ 6-1
Forward Parallel Loopback.........................................................................................................................6-2
PIPE Reverse Parallel Loopback.................................................................................................................6-3
Reverse Serial Loopback..............................................................................................................................6-4
Reverse Serial Pre-CDR Loopback............................................................................................................ 6-5
Document Revision History....................................................................................................................... 6-6
Dynamic Reconguration in Cyclone V Devices............................................... 7-1
Dynamic Reconguration Features...........................................................................................................7-1
Oset Cancellation.......................................................................................................................................7-2
Transmitter Duty Cycle Distortion Calibration.......................................................................................7-3
PMA Analog Controls Reconguration................................................................................................... 7-3
Dynamic Reconguration of Loopback Modes....................................................................................... 7-4
Transceiver PLL Reconguration ..............................................................................................................7-4
Transceiver Channel Reconguration.......................................................................................................7-5
Transceiver Interface Reconguration ..................................................................................................... 7-5
Reduced .mif Reconguration ...................................................................................................................7-6
Unsupported Reconguration Modes.......................................................................................................7-7
Document Revision History....................................................................................................................... 7-7
TOC-4
Cyclone V Device Handbook Volume 2: Transceivers
Altera Corporation

5CSEBA5U23C6N 数据手册

Intel(英特尔)
93 页 / 0.9 MByte
Intel(英特尔)
44 页 / 0.67 MByte
Intel(英特尔)
171 页 / 1.73 MByte

5CSEBA5U23C6 数据手册

Altera(阿尔特拉)
FPGA - 现场可编程门阵列 Cyclone V SE dual -core ARM Cortex-A9
Intel(英特尔)
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