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AD7788BRMZ-REEL 其他数据使用手册 - ADI（亚德诺）
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ADI（亚德诺）
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AD转换器
封装:
MSOP-10
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低功耗， 16位/ 24位Σ-Δ型ADC Low Power, 16-/24-Bit, Sigma-Delta ADCs
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AD7788BRMZ-REEL数据手册
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–3–
Table I.
Model HBM MM Socketed CDM
Simulate Human Body Machine Charged Device
Origin US Military Japan 1976 AT&T 1974
Late 1960s
Real World Yes Generally No Yes
RC 1.5 kΩ, 100 pF 0 Ω, 200 pF 1 Ω , 1 pF–20 pF
Rise Time <10 ns 14 ns* 400 ps**
I
PEAK
at 400 V 0.27 A 5.8 A* 2.1 A**
Package
Dependent No No Yes
Leakage
Recovery No No Yes
* These values are per ESD Association Standard S5.2. EIAJs stan-
dard ED-4701 Method C-111 includes no waveform specifications.
** These values are for the direct charging (socketed) method.
Prevention
When auditing a facility in which ESD protective mea-
sures will be taken, the following should be considered:
4
• There must be a grounded workbench on which to
handle static sensitive devices incorporating:
a) Personal ground strap (wrist strap)
b) Conductive trays or shunts, etc.
c) Conductive work surface
d) Conductive floor or mat
e) A common ground point
• All steel shelving or cabinets used to store devices
must be grounded.
• The relative humidity should be controlled; the desir-
able range is 40 to 60 percent. Where high relative
humidity levels cannot be maintained, the use of ion-
ized air should be used to dissipate electrostatic
charges.
• All electrical equipment used in the area must be
grounded.
• Prohibit the use of prime static generators, e.g.,
Scotch tape.
• Follow up with ESD audits at a minimum of three
month intervals.
• Training: Keep in mind, the key to an effective ESD
control program is “TRAINING.” Training should be
given to all personnel who come in contact with inte-
grated circuits and should be documented for certifi-
cation purposes, e.g., ISO 9000 audits.
Determining whether a device failed as a result of ESD
or Electrical Overstress (EOS) can be difficult and is of-
ten best left to Failure Analysis Engineers. Typically
ESD damage is less obvious than that of EOS when elec-
trical analysis and internal visual analysis are
performed. In the case of ESD, events of 1 kV or more
(depending on the ESD rating of the device) can rupture
oxides (inter layer dielectric of the die) and damage
junctions in less than 10 ns (see Figure 6). Alternately,
EOS conditions leading to 1 to 3 amps of current for a
duration of ≥1 ms can cause sufficient self-heating of
bond wires to fuse them. Such conditions can occur as a
result of latch-up. Lower currents can cause rapid melt-
ing of chip metallization and other interconnect layers
(see Figure 5).
Figure 5. Scanning Electron Microscope View of a
Fused Metallization Site, as a Result of Electrical
Overstress
Figure 6. Scanning Electron Microscope Cross-
Sectional View of a CDM ESD Site. This subsurface site
could not be viewed from the surface with an optical
microscope.
JEDEC
JS-001-2011
JEDEC
JESD22-C101E
JEDEC
JESD22-A115B
(Standard
Test Method)
Witha400Vchargingvoltage,asocketedCDMdisͲ
chargewillhaveapeakcurrentofbetween2Aand
8Adependingonpackagetype.However,thevery
shortdurationoftheoverallCDMeventresultsinan
overalldischargeofrelativelylowenergy.
SummaryofESDModels
Table
Iisarefe
rencetablethatcomparesthemost
importantcharacteristicsofthethreeESDsimulation
models.
Standard
Document
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