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ATMEGA164PV-10PU 其他数据使用手册 - ATMEL（爱特美尔）
制造商:
ATMEL（爱特美尔）
分类:
8位微控制器
封装:
DIP-40
描述:
ATMEL ATMEGA164PV-10PU 微控制器, 8位, ATmega, 10 MHz, 16 KB, 1 KB, 40 引脚, DIP
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P2P4P74P93P111P139Hot
原理图在P3P9P72P93P94P96P97P112P117P118P120P122
封装尺寸在P423P424P425
型号编码规则在P420P421P422
封装信息在P423
应用领域在P41P50P62P65P276P280P293P294
导航目录
ATMEGA164PV-10PU数据手册
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5
8011G–AVR–08/07
ATmega164P/324P/644P
2.3.3 Port A (PA7:PA0)
Port A serves as analog inputs to the Analog-to-digital Converter.
Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port A pins that are externally pulled low will source current if
the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega164P/324P/644P as
listed on page 80.
2.3.4 Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega164P/324P/644P as
listed on page 82.
2.3.5 Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of the JTAG interface, along with special features of the
ATmega164P/324P/644P as listed on page 85.
2.3.6 Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega164P/324P/644P as
listed on page 87.
2.3.7 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset
Characteristics” on page 331. Shorter pulses are not guaranteed to generate a reset.
2.3.8 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
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