Datasheet 搜索 > 微控制器 > Microchip（微芯） > PIC16F1779T-I/MV 数据手册 > PIC16F1779T-I/MV 其他数据使用手册 4/11 页
器件3D模型￥ 7.316
PIC16F1779T-I/MV 其他数据使用手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
UQFN-40
描述:
PIC 32MHz 闪存：16K@x14bit RAM：2KB
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
PIC16F1779T-I/MV数据手册
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若手册格式错乱，请下载阅览PDF原文件
PIC16(L)F1777/8/9
DS80000676A-page 4 2015 Microchip Technology Inc.
2.3 SPI Slave Mode
When the MSSP module is configured with either
of the Slave modes listed below and Sleep is
executed during transmission, the WCOL bit is
erroneously set. Although the WCOL bit is set, it
does not cause a break in transmission or
reception.
Mode 1: SPI Slave mode with SS
disabled
(SSPM = 0101) and CKE = 0.
Mode 2: SPI Slave mode with SS
enabled
(SSPM = 0100) and SS
not set and then
cleared before each consecutive
transmission. This typically occurs during
multiple byte transmissions in which the
master does not release the SS line until
all transmission has completed.
Work around
Method 1: The WCOL bit can be ignored since the
issue does not interfere with MSSP
hardware.
Method 2: Clear the SSPEN bit after each
transaction, then set SSPEN before next
transaction.
Affected Silicon Revisions
3. Module: Programmable Ramp Generator
(PRG)
3.1 Timing Sources
The Configurable Logic Cell (CLC) timing sources
LC1_out, LC2_out, LC3_out, and LC4_out as
defined in Table 30-5 of the data sheet are not
available in the A0 revision. Use of these
resources will result in unexpected operation.
Work around
None.
Affected Silicon Revisions
4. Module: ECCP
4.1 Compare Mode
The ECCP Compare Toggle mode
(CCP1M<3:0> bits = 0010) works properly as long
as the Timer1 Prescaler value is configured to 1:1.
When the Timer1 prescaler value is configured to
any other value, the ECCP compare output yields
unexpected results.
Work around
Only use the Compare Toggle mode when the
Timer1 Prescaler value is set to 1:1.
Affected Silicon Revisions
A0
X
A0
X
A0
X
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