Datasheet 搜索 > 微处理器 > NXP（恩智浦） > MPC8313CVRAFFC 数据手册 > MPC8313CVRAFFC 用户编程技术手册 6/28 页
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MPC8313CVRAFFC 用户编程技术手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微处理器
封装:
PBGA-516
描述:
NXP MPC8313CVRAFFC 芯片, 微控制器, 32位, POWER, 333MHZ, TEPBGA-II-516
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MPC8313CVRAFFC数据手册
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Programming the User-Programmable Machine (UPM) for SDRAM Memory Devices, Rev. 0
6 Freescale Semiconductor
SDRAM Usage
2.1 SDRAM Commands
Table 2 describes the SDRAM commands used with eLBC devices.
2.2 SDRAM Access Cycles
This section includes the following subsections:
• Section 2.2.1, “Initialization”
• Section 2.2.2, “Mode Register Setting”
Table 2. SDRAM Commands
Command Description
A[0:9]
SD
,
A11
SD
A10
SD
CS RAS CAS WE
ACTIVATE Bank activate command. Row addresses are latched on A[0:10]
SD
.
A further command cannot be issued until t
RCD
is met.
V
1
1
Valid address
VLLHH
PRECHARGE
ALL
Precharge all. Precharges both banks simultaneously, then switches
to the idle state. A further command cannot be issued until t
RP
is met.
X
2
2
No effect
HLLHL
WRITE Write. Performs a write access to the bank selected by bank select
(BS
SD
). The data is latched on the positive edge of CLK. The burst
length and the addressing mode are programmed in the mode
register at power-up before the write operation.
V
1
LLHLL
WRITEA Write with autoprecharge (AP). Performs a write command with a
precharge operation automatically after the write operation. This
command cannot be interrupted by any other command. A further
command cannot be issued until t
RP
is met.
V
1
HLHLL
READ Read. Performs a read access to the bank selected by BS. The data
is issued on the positive edge of CLK at a time defined by the CAS
latency.
V
1
LLHLH
READA Read with autoprecharge (AP). Performs a READ command with a
precharge operation automatically after the write operation. This
command cannot be interrupted by any other command. A further
command cannot be issued until t
RP
is met.
V
1
HLHLH
MRS Mode register set. Programs CAS latency, addressing mode, and
burst length in the mode register, which must be configured after
power-up because after reset, the mode register is undefined. A
further command cannot be issued until t
RSC
is met.
V
1
V
1
LL LL
NOP No-operation. Performs no operation (the same as device deselect). X
2
X
2
LH HH
AUTOREFRESH Autorefresh. Refreshes the row address provided by the internal
refresh counter. A further command cannot be issued until t
RC
is met.
X
2
X
2
LL LH
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