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器件3D模型￥ 54.207
AT89C51RD2-SLSUM 开发手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
PLCC-44
描述:
AT89C51 系列 60 MHz 64 KB 闪存 2 KB SRAM 8 位 微控制器 - PLCC-44
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
AT89C51RD2-SLSUM数据手册
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P89V51RD2 and In-Application Programming (IAP)
J
an
W
ac
lawe
k
,
w
e
k
@
ef
t
on
.s
k
Int
roduct
ion
T
he
P
8
9V
51
RD
2
1
is
a
n
8
0
51
/
8
05
2
-
pin-c
o
m
pat
i
b
l
e
micr
o
c
o
n
t
r
o
l
l
e
r
b
y
N
X
P
(
e
x
-
P
hi
lip
s
)
,
w
it
h
6
4
+
8
kB
FLAS
H
code
me
m
ory
,
7
6
8B
i
nt
e
r
nal
R
AM
(
E
R
A
M
/
X
R
A
M)
,
6
-c
lo
c
k
(
x
2)
mo
de
,
a
nd
a
c
o
uple
o
f
e
xtend
e
d
pe
r
i
phe
ra
ls,
s
uc
h
a
s
the
P
C
A
u
nit
,
S
P
I
interfac
e
a
nd
w
atc
hdo
g
c
ou
nt
e
r.
T
he
m
os
t
re
m
ar
k
ab
l
e
fe
atur
e
i
s
,
ho
w
e
ve
r
,
t
hat
it'
s
F
L
AS
H
c
an
b
e
i
n-
s
i
t
u
p
r
o
gramme
d
(
I
SP
)
t
hroug
h
U
AR
T;
a
nd
al
s
o
its
s
e
l
f-
programm
ab
i
l
i
t
y
(
in-
ap
pl
icat
i
o
n
p
r
o
gramm
ab
i
l
i
ty,
I
A
P
)
.
T
he
P
8
9
V51
R
D
2
i
s
a
s
uc
c
e
s
s
o
r
t
o
the
s
uc
c
e
s
s
f
ul
P
89
C
5
1
R
D
+
2
/
P
89C51
R
D
2
3
li
ne
,
w
hi
c
h
intr
o
duc
e
d
the
I
S
P
/
I
A
P
paradig
m
t
o
t
he
hig
her-
e
nd
FL
AS
H-bas
e
d
8-
b
it
mi
c
r
o
c
o
nt
r
o
l
l
ers
.
Mic
rocontr
o
l
l
e
r
s
w
ith
v
e
r
y
s
im
i
l
ar
fe
at
ur
e
s
-
8
0
51
-
pi
n-
c
o
mpat
i
b
l
e
,
w
i
t
h
up
t
o
6
4
k
B
of
F
LAS
H
,
s
up
p
o
r
ti
ng
I
A
P
a
nd
I
S
P
-
are
ma
n
u
fac
tur
e
d
b
y
m
ul
t
ip
l
e
m
a
n
u
fac
t
ure
r
s
,
i
nc
lud
ing
NX
P
'
s
o
w
n
P8
9
C
6
6
x/
P
8
9
V6
6x
4
,
Atme
l
A
T89
C
5
1
R
D
2
/
AT89
C
5
1
ED
2
5
(
s
uc
c
e
s
sor
to
the
Te
mi
c
T8
9C51
R
D
2
)
,
Nu
voton
(
e
x-
W
inbo
nd)
W7
8
ER
D
2
A
6
a
nd
S
S
T
S
S
T8
9
E5
64
R
D
/
SS
T8
9
E5
1
6RD
7
.
So
me
of
t
he
m
offe
r
als
o
a
m
i
x
o
f
m
ode
l
s
with
le
s
s
FLASH
(
a
nd
At
m
el
als
o
a
mo
de
l
w
i
t
h
1
28
k
B
F
LAS
H,
the
A
T8
9
C
5
1
R
E2
)
a
nd
3
V
s
up
pl
y
v
o
ltag
e
.
How
e
v
e
r,
al
t
ho
ug
h
t
he
y
ar
e
r
e
m
ar
kabl
y
s
im
i
l
ar
,
the
y
u
s
u
all
y
s
i
gni
fic
antly
di
ffer
in
the
I
A
P/
I
S
P
me
thod.
So
me
e
ve
n
do
n'
t
h
a
ve
f
act
o
r
y-
i
ns
t
al
l
e
d
b
oo
t
l
o
ad
e
r
,
e
v
e
n
if
t
he
y
us
u
al
ly
offe
r
f
ree
bo
o
t
l
o
ad
e
r
firm
w
ar
e
a
nd
ass
oc
i
a
t
e
d
P
C
s
oftw
are.
A
s
P
hi
l
i
ps/
N
X
P
p
has
e
d
out
t
he
P
8
9C5
1
R
D
2
i
n
f
a
vour
of
P
8
9
V51
R
D
2
,
u
s
e
rs
s
tar
te
d
t
o
comp
l
a
in
about
the
r
athe
r
d
iffe
r
e
nt
n
at
ure
of
the
I
A
P
proced
ur
e
in
the
l
at
t
er.
T
his
m
ade
N
X
P
t
o
i
nt
rod
uc
e
the
P
8
9C
V
5
1
R
D
2
8
a
nd
f
ami
ly,
w
hi
c
h
,
al
t
ho
ugh
p
h
y
sic
al
ly
c
l
o
s
e
r
t
o
t
he
n
e
wer
P
8
9V5
1
R
D
2,
m
i
m
ic
s
c
lo
s
e
r
t
he
orig
inal
I
A
P
be
ha
v
i
our
of
the
o
ld
e
r
P
8
9
C51
R
D
2
.
Family members
There are also modifications to P89V51RD2 offered by NXP, besides the three packaging options
(traditional DIP40 and PLCC44, and the miniscule TQFP44 with 0.8mm pin pitch).
Devices with less FLASH are marked as P89V51RB2 for 16kB FLASH and P89V51RC2 for 32kB FLASH.
Low supply voltage (3V) devices are marked as "LV", such as in P89LV51RD2
9
. Unfortunately, NXP
currently does not offer wide supply voltage devices in this family.
As most of the characteristics are the same across the whole family, often, "cumulative" marking such as
"P89V51Rx2" is used to denote any member of the family. However, throughout this document,
"P89V51RD2" will be used consistently, marking also other members of the family as appropriate.
There were several versions of the P89V51RD2 datasheet issued by Philips/NXP. To avoid confusion, it is
always a good idea to download the latest one. At the time of writing of this document, the latest
datasheet is marked as "Rev.4 - 1. May 2007"
1
0
.
P
89V
51RD
2
a
nd
IS
P
O
ne
of
the
k
e
y
m
o
me
nt
s
of
s
uc
c
e
s
s
o
f
t
he
P
8
9V5
1
R
D
2
'
s
p
r
e
de
c
e
s
s
or
s
w
a
s
t
he
ab
il
i
t
y
t
o
p
r
o
g
r
am
t
he
m
in-
s
i
t
u
thr
o
ug
h
U
A
R
T.
T
his
al
le
via
t
e
d
t
he
n
e
e
d
fo
r
a
cos
tly
parall
e
l
d
evice
p
r
o
g
r
am
m
er,
o
r
e
v
e
n
a
s
pe
c
i
a
l
is
ed
prog
r
am
m
i
ng
"
cable
";
w
hi
c
h
made
t
he
s
e
micr
o
c
ontr
o
l
l
e
r
s
att
rac
t
ive
for
s
m
al
l
ente
r
p
r
i
s
e
s
a
nd
hobb
y
i
s
ts
,
de
s
p
i
t
e
thei
r
hig
he
r
pric
e
.
It
als
o
all
ow
s
e
as
y
fie
l
d-
u
pd
at
e
of
fi
r
m
w
ar
e
fr
o
m
a
n
y
P
C
o
r
other
de
v
i
c
e
e
qui
p
p
e
d
w
ith s
t
and
ar
d
s
e
r
i
al
p
ort
.
T
he
P
8
9
V5
1
R
D
2
c
ontinue
d
i
n
t
hi
s
trend
,
al
t
ho
ugh
w
ith
a
s
l
ight
l
y
d
iffe
r
e
nt
c
om
mu
nicat
i
on
prot
oc
o
l
,
a
nd,
more
imp
ortant
ly,
a
d
i
ffe
rent
b
o
o
tl
o
a
de
r
e
nt
r
y
me
t
ho
d
.
O
n
the
ol
d
er
mo
d
e
l
s
,
bo
ot
l
o
a
de
r
w
a
s
ente
r
e
d
w
h
e
n
a p
ar
ticular
s
e
t
o
f
v
o
ltag
e
le
ve
ls
w
as
ap
pl
i
e
d
t
o
v
a
rio
us
p
ins
(inc
lud
ing
t
he
P
S
E
N/
p
in)
.
O
n
P
8
9
V51
R
D
2
,
aft
e
r
r
e
s
e
t,
t
he
bo
ot
l
o
a
de
r
w
aits
fo
r
a
p
r
e
de
t
e
rm
ine
d
t
i
m
e
,
u
nt
i
l
a
"
U
"
c
h
arac
te
r
(5
5
h
)
ar
rive
s
t
o
t
he
U
AR
T
recei
v
e
r.
T
he
d
at
as
he
e
t
s
tat
e
s
this
tim
e
as
"
ap
p
r
o
x
i
mat
e
ly
40
0
ms"
,
ho
w
e
v
e
r
,
as
i
t
is
in
f
act
de
rived
fr
o
m
the
w
at
c
hdo
g
,
this
t
i
m
e
is
d
e
pe
nde
nt
on
t
he
s
y
s
te
m
c
l
oc
k
fr
e
que
nc
y
,
b
e
ing
a
rou
nd
4
0
0
m
s
w
h
e
n
f
C
L
K
is
ap
prox.
3
.
5
M
H
z;
for
o
t
he
r
clock
f
re
que
nc
ie
s
this
time
i
s
p
r
o
p
ort
i
o
na
t
e
ly
s
hort
e
r
or
long
e
r
.
1
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