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MC9S12DP512CPVE 开发手册 - NXP（恩智浦）
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NXP（恩智浦）
分类:
16位微控制器
封装:
LQFP-112
描述:
NXP MC9S12DP512CPVE 微控制器, 16位, S12D, 25 MHz, 512 KB, 14 KB, 112 引脚, LQFP
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MC9S12DP512CPVE数据手册
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Freescale Semiconductor
Application Note
Document Number: AN3469
Rev. 1, 07/2007
Contents
© Freescale Semiconductor, Inc., 2007. All rights reserved.
1 Introduction
The MC9S12XEP100 provides significant performance
improvements over the existing 9S12 family through a
combination of increased clock speed and enhanced
functionality. Existing S12 users can take advantage of
the S12XE family’s increased speed of operation almost
immediately due to its high level of backwards
compatibility. Further performance benefits can be
gained by optimizing the application design to take
advantage of the new feature set.
This document describes the notable differences between
the S12 family and the S12XE family. Developers
currently designing applications with the S12 family
should note these differences so they can take advantage
of the S12XE when appropriate. A companion
application note (AN2615) describes the compatibility
between the S12 and the S12XD families.
All differences noted are based on the feature set of the
9S12XEP100. Other derivatives of the S12XE family
might not feature all of the functions described here.
Refer to the appropriate data sheet for details.
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 S12XE Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Software Architecture. . . . . . . . . . . . . . . . . . . . . . 2
2.2 CPU and Instruction Set. . . . . . . . . . . . . . . . . . . . 3
2.3 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 System Integrity Improvements through Memory
Management9
2.5 XGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6 NVM – Flash and EEPROM. . . . . . . . . . . . . . . . 14
2.7 Memory Management Controller . . . . . . . . . . . . 15
2.8 Expanded Bus interface . . . . . . . . . . . . . . . . . . . 18
2.9 Analog to Digital Converter (ATD) . . . . . . . . . . . 19
2.10 Debug Module . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.11 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.12 Internal Phase Locked Loop (IPLL) . . . . . . . . . . 22
2.13 Enhanced Capture Timer . . . . . . . . . . . . . . . . . . 23
2.14 Real Time Interrupt . . . . . . . . . . . . . . . . . . . . . . 24
2.15 COP — Watchdog . . . . . . . . . . . . . . . . . . . . . . . 24
2.16 Periodic Interrupt Timer . . . . . . . . . . . . . . . . . . . 24
2.17 Miscellaneous Modules . . . . . . . . . . . . . . . . . . . 25
2.18 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . 26
2.19 IIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.20 Serial Peripheral Interface (SPI) . . . . . . . . . . . . 28
3 Considerations for Existing S12 Applications . . . . . . . . 28
3.1 General Comments . . . . . . . . . . . . . . . . . . . . . . 28
3.2 CPU and Instruction Set. . . . . . . . . . . . . . . . . . . 28
3.3 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . 29
3.4 Memory Configuration and Access . . . . . . . . . . 30
3.5 Expanded Bus interface . . . . . . . . . . . . . . . . . . . 32
3.6 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.7 TEST and Reset Pins. . . . . . . . . . . . . . . . . . . . . 33
3.8 Background Debug Module . . . . . . . . . . . . . . . . 33
3.9 Debug Module . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.10 Backwards Compatible Modules . . . . . . . . . . . . 34
3.11 Unchanged Modules . . . . . . . . . . . . . . . . . . . . . 35
S12 and S12XE Family
Compatibility
by: Steve McAslan, MCD Applications, East Kilbride
Joachim Krücken, Microcontroller Division, Munich
Martyn Gallop, MCD Applications, East Kilbride
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