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MCP2122T-E/SN 开发手册 - Microchip（微芯）
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Microchip（微芯）
分类:
接口芯片
封装:
SOIC-8
描述:
MCP2122系列 115.2k波特率 低功耗模式 红外编码器/解码器-SOIC-8
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MCP2122T-E/SN数据手册
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2004 Microchip Technology Inc. DS00946A-page 1
AN946
INTRODUCTION
The MCP2122 has up to four signals that can be inter-
faced to the embedded systems Host Controller. These
signals are the transmitted and received data (TX and
RX), the 16XCLK signal and the RESET signal.
The MCP2122 is pinout compatible with the Agilent
®
HSDL-7000 Encoder/Decoder.
The 16x clock is used for the baud clock timing (trans-
mit and receive). There are 16 16x clocks (16XCLK) for
each bit time. In systems that have already been
designed with the HSDL-7000, the 16XCLK signal is
already present. For systems that are to be designed,
the generation of a 16x clock signal will need to be
done. For embedded systems using a PICmicro
®
microcontroller unit (MCU) as the Host Controller, the
Capture/Compare/PWM (CCP) and Timer2 modules
can be used to generate the 16XCLK signal. This is
accomplished using the CCP module in PWM mode.
This application note will discuss methods with which
to interface the MCP2122 to a Host Controller and how
to use the PICmicro MCU’s CCP and Timer2 modules
to generate the 16XCLK signal.
FIGURE 1: TYPICAL MCP2122 SYSTEM BLOCK DIAGRAM
Author: Mark Palmer
Microchip Technology Inc.
Encode
Decode
TX
TXIR
RX
RXIR
RESET
MCP2122
PICmicro
®
SO
SI
TFDU 4100
UART
TXD
RXD
Reset
Logic
Clock
Logic
16XCLK
Clock
Host UART
Interface
IR
Interface
Host Controller Protocol Handler Optical
Transceiver
(I/O or CCPx)
MCU
Interfacing the MCP2122 to the Host Controller
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