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P4080DS-PC 开发手册 - NXP（恩智浦）
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Freescale Semiconductor
Application Note
© Freescale Semiconductor, Inc., 2009. All rights reserved.
The products described in this document are microprocessor
cores built on Power Architecture™ technology. This
application note outlines the differences between the
registers implemented in the e300 core (MPC603e
processor) and the e500 microprocessor core. It also
discusses the differences between the register models
defined by the Apple/IBM/Motorola (AIM) version and
those defined by the Power instruction set architecture
(Power ISA).
Registers defined by both the AIM version of the PowerPC
architecture and Power ISA are identified by the level of the
architecture at which the register is defined, as follows:
• Book I, user instruction set architecture (UISA)
• Book II, virtual environment architecture (VEA)
• Book III or III-E (Book III for AIM, Book III-E for
Power ISA), operating environment architecture
(OEA)
• Book IV, implementation definition
In addition, Power ISA also includes a fourth book, called
Book VLE, which contains additional definitions. Neither
the e300 or the e500 cores contain registers defined by Book
VLE.
Contents
1 Migrating from PowerPC AIM Architecture to Power
ISA Register Model . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Special-Purpose Registers by SPR Number . . . . . . . . 4
3 Special-Purpose Registers by SPR Abbreviation . . . 13
4 Architecture-Defined Non-SPR Registers by
Abbreviation .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 F
reescale EIS-Defined Performance Monitor Registers
(PMRs) .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
e300 (MPC603e) and e500
Register Model Comparison
Document Number: AN2490/D
Rev. 1, 09/2009
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