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SRC4190-Q1
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SRC4190-Q1数据手册
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MODE [2:0]
IFMT [2:0]
OFMT [1:0]
OWL [1:0]
MUTE
BYPAS
LGRP
RST
Control
Logic
Rate
Estimator
LRCKI
LRCKO
REFCLK
RDY
LRCKO
BCKO
SDOUT
TDMI
Audio
Output
Port
RCKI REFCLK
Reference
Clock
LRCKI
BCKI
SDIN
Audio
Input
Port
Interpolation
Filters
16f
SIN
f
SIN
f
SOUT
V
DD
DGND
V
IO
DGND
Re-Sampler
16f
SOUT
Decimation
Filters
Power
SRC4190-Q1
www.ti.com
SBFS034A SEPTEMBER 2008REVISED OCTOBER 2009
Figure 1. Functional Block Diagram
Reference Clock
The SRC4190 requires a reference clock for operation. The reference clock is applied at the RCKI input, pin 2.
Figure 2 illustrates the reference clock connections and requirements for the SRC4190. The reference clock may
operate at 128f
S
, 256f
S
, or 512f
S
, where f
S
is the input or output sampling frequency. The maximum external
reference clock input frequency is 50 MHz.
Figure 2. Reference Clock Input Connections and Timing Requirements
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 17
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