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STM32F373V8H6 数据手册 - ST Microelectronics（意法半导体）
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ST Microelectronics（意法半导体）
分类:
微控制器
封装:
BGA-100
描述:
STMICROELECTRONICS STM32F373V8H6 微控制器, 32位, 16Σ-Δ模数转换器, ARM 皮质-M4F, 72 MHz, 64 KB, 16 KB, 100 引脚, BGA
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STM32F373V8H6数据手册
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STM32F373xx Functional overview
47
3.21 Serial peripheral interface (SPI)/Inter-integrated sound
interfaces (I
2
S)
Three SPIs are able to communicate at up to 18 Mbits/s in slave and master modes in full-
duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The SPIs can be served by the DMA controller.
Three standard I
2
S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available, that can
be operated in master or slave mode. These interfaces can be configured to operate with
16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up
to 192 kHz are supported. When either or both of the I
2
S interfaces is/are configured in
master mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency. All I2S interfaces can operate in half-duplex mode only.
Refer to Table 9 for the features between SPI1, SPI2 and SPI3.
3.22 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC
controller to wakeup the MCU from Stop mode on data reception.
3.23 Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
Table 9. STM32F373xx SPI/I2S implementation
SPI features
(1)
1. X = supported.
SPI1 SPI2 SPI3
Hardware CRC calculation X X X
Rx/Tx FIFO X X X
NSS pulse mode X X X
I2S mode XXX
TI mode XXX
I2S full-duplex mode - - -
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