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5CSEBA5U19C7N 其他数据使用手册 - Intel（英特尔）
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Intel（英特尔）
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5CSEBA5U19C7N数据手册
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Resetting the Transmitter with the User-Coded Reset Controller During Device Power-
Up ................................................................................................................................................ 3-7
Resetting the Transmitter with the User-Coded Reset Controller During Device
Operation.....................................................................................................................................3-8
Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up
Conguration..............................................................................................................................3-9
Resetting the Receiver with the User-Coded Reset Controller During Device Operation..3-10
Transceiver Reset Using Avalon Memory Map Registers.....................................................................3-11
Transceiver Reset Control Signals Using Avalon Memory Map Registers.............................3-11
Clock Data Recovery in Manual Lock Mode......................................................................................... 3-12
Control Settings for CDR Manual Lock Mode.......................................................................... 3-13
Resetting the Transceiver in CDR Manual Lock Mode............................................................ 3-13
Resetting the Transceiver During Dynamic Reconguration..............................................................3-14
Guidelines for Dynamic Reconguration if Transmitter Duty Cycle Distortion
Calibration is Required During Device Operation..............................................................3-14
Transceiver Blocks Aected by the Reset and Powerdown Signals.....................................................3-15
Transceiver Power-Down..........................................................................................................................3-16
Document Revision History.....................................................................................................................3-16
Transceiver Protocol Congurations in Cyclone V Devices.............................. 4-1
PCI Express................................................................................................................................................... 4-2
PCIe Transceiver Datapath............................................................................................................. 4-3
PCIe Supported Features.................................................................................................................4-4
PCIe Supported Congurations and Placement Guidelines...................................................... 4-7
Gigabit Ethernet......................................................................................................................................... 4-13
Gigabit Ethernet Transceiver Datapath.......................................................................................4-15
XAUI............................................................................................................................................................4-19
Transceiver Datapath in a XAUI Conguration........................................................................4-20
XAUI Supported Features.............................................................................................................4-21
Transceiver Clocking and Channel Placement Guidelines in XAUI Conguration............ 4-24
Serial Digital Interface...............................................................................................................................4-26
Congurations Supported in SDI Mode..................................................................................... 4-27
Serial Digital Interface Transceiver Datapath............................................................................ 4-29
Serial Data Converter (SDC) JESD204................................................................................................... 4-30
SATA and SAS Protocols...........................................................................................................................4-31
Deterministic Latency Protocols—CPRI and OBSAI...........................................................................4-32
Latency Uncertainty Removal with the Phase Compensation FIFO in Register Mode....... 4-33
Channel PLL Feedback for Deterministic Relationship........................................................... 4-33
CPRI and OBSAI............................................................................................................................4-33
6.144-Gbps Support Capability in Cyclone V GT Devices.......................................................4-36
CPRI Enhancements......................................................................................................................4-37
Document Revision History.....................................................................................................................4-38
Transceiver Custom Congurations in Cyclone V Devices............................... 5-1
Standard PCS Conguration...................................................................................................................... 5-1
Custom Conguration Channel Options..................................................................................... 5-2
Rate Match FIFO in Custom Conguration................................................................................ 5-5
Cyclone V Device Handbook Volume 2: Transceivers
TOC-3
Altera Corporation
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