器件3D模型

￥ 56.701

AD977AARSZ 其他数据使用手册 - ADI（亚德诺）

制造商:

ADI（亚德诺）

分类:

AD转换器

封装:

SSOP-28

描述:

ANALOG DEVICES AD977AARSZ 模数转换器, 16 bit, 200 kSPS, 单, 4.75 V, 5.25 V, SSOP

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符号图

焊盘图

引脚图

产品图

页面导航:

引脚图在P10P11P22Hot

原理图在P1

封装尺寸在P54

型号编码规则在P54

功能描述在P4P10P11P21

技术参数、封装参数在P1P5P6P7P8P9

应用领域在P1

电气规格在P12

导航目录

引脚图在P10 P11 P22
原理图在P1
封装尺寸在P54
型号编码规则在P54
功能描述在P4 P10 P11 P21
技术参数、封装参数在P1 P5 P6 P7 P8 P9
应用领域在P1
电气规格在P12

AD977AARSZ数据手册

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14-Bit, 160 MSPS, 2×/4×/8× Interpolating

Dual TxDAC+

Digital-to-Analog Converter

AD9775

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

14-bit resolution, 160 MSPS/400 MSPS input/output

data rate

Selectable 2×/4×/8× interpolating filter

Programmable channel gain and offset adjustment

/4, f

/8 digital quadrature modulation capability

Direct IF transmission mode for 70 MHz + IFs

Enables image rejection architecture

Fully compatible SPI® port

Excellent ac performance

SFDR: −71 dBc @ 2 MHz to 35 MHz

W-CDMA ACPR: −71 dB @ IF = 19.2 MHz

Internal PLL clock multiplier

Selectable internal clock divider

Versatile clock input

Differential/single-ended sine wave or TTL/CMOS/LVPECL

compatible

Versatile input data interface

Twos complement/straight binary data coding

Dual-port or single-port interleaved input data

Single 3.3 V supply operation

Power dissipation: 1.2 W @ 3.3 V typical

On-chip, 1.2 V reference

80-lead, thin quad flat package, exposed pad (TQFP_EP)

APPLICATIONS

Communications

Analog quadrature modulation architecture

3G, multicarrier GSM, TDMA, CDMA systems

Broadband wireless, point-to-point microwave radios

Instrumentation/ATE

FUNCTIONAL BLOCK DIAGRAM

161616

/2 /2

AD9775

DATA

ASSEMBLER

LATCH

MUX

CONTROL

SPI INTERFACE AND

CONTROL REGISTERS

HALF-BAND FILTERS ALSO CAN BE

CONFIGURED FOR ZERO STUFFING ONLY

I AND Q

NONINTERLEAVED

OR INTERLEAVED

DATA

CLOCK OUT

WRITE

SELECT

HALF-

BAND

FILTER1*

FILTER

BYPASS

MUX

IMAGE

REJECTION/

DUAL DAC

MODE

BYPASS

MUX

I/Q DAC

GAIN/OFFSET

REGISTERS

HALF-

BAND

FILTER2*

HALF-

BAND

FILTER3*

COS

IDAC

VREF

IOFFSET

GAIN

DAC

DIFFERENTIAL

CLK

OFFSET

DAC

COS

OUT

PRESCALER

PLL CLOCK MULTIPLIER AND CLOCK DIVIDER

PHASE DETECTOR

AND VCO

SIN

DAC

/2, 4, 8

(

DAC

)

02858-001

Figure 1.

WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW

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AD977AARSZ 数据手册

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AD977AARSZ 其他数据使用手册

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AD977AARSZ 开发手册

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6 页 / 0.9 MByte

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AD977AARSZ 数据手册

ADI（亚德诺）

ANALOG DEVICES AD977AARSZ 模数转换器, 16 bit, 200 kSPS, 单, 4.75 V, 5.25 V, SSOP

AD9776ABSVZ 数据手册

ADI（亚德诺）

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AD977AARZ 数据手册

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ANALOG DEVICES AD977AARZ 模数转换器, 16 bit, 200 kSPS, 单, 4.75 V, 5.25 V, WSOIC

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