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ADC0808CCN 其他数据使用手册 - National Semiconductor（美国国家半导体）
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National Semiconductor（美国国家半导体）
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DIP
描述:
8通道多路复用8位向上兼容A / D转换器 8-Bit uP Compatible A/D Converters with 8-Channel Multiplexer
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ADC0808CCN数据手册
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Electrical Characteristics (Continued)
Digital Levels and DC Specifications: ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75≤V
CC
≤5.25V,
−40˚C≤T
A
≤+85˚C unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
DATA OUTPUTS AND EOC (INTERRUPT)
V
OUT(1)
Logical “1” Output Voltage V
CC
=
4.75V
I
OUT
=
−360µA
I
OUT
=
−10µA
2.4
4.5
V(min)
V(min)
V
OUT(0)
Logical “0” Output Voltage I
O
=
1.6 mA 0.45 V
V
OUT(0)
Logical “0” Output Voltage EOC I
O
=
1.2 mA 0.45 V
I
OUT
TRI-STATE Output Current V
O
=
5V 3 µA
V
O
=
0−3 µA
Electrical Characteristics
Timing Specifications V
CC
=
V
REF(+)
=
5V, V
REF(−)
=
GND, t
r
=
t
f
=
20 ns and T
A
=
25˚C unless otherwise noted.
Symbol Parameter Conditions MIn Typ Max Units
t
WS
Minimum Start Pulse Width (
Figure 5
) 100 200 ns
t
WALE
Minimum ALE Pulse Width (
Figure 5
) 100 200 ns
t
s
Minimum Address Set-Up Time (
Figure 5
)2550ns
t
H
Minimum Address Hold Time (
Figure 5
)2550ns
t
D
Analog MUX Delay Time R
S
=
0Ω (
Figure 5
) 1 2.5 µs
From ALE
t
H1
,t
H0
OE Control to Q Logic State C
L
=
50 pF, R
L
=
10k (
Figure 8
) 125 250 ns
t
1H
,t
0H
OE Control to Hi-Z C
L
=
10 pF, R
L
=
10k (
Figure 8
) 125 250 ns
t
c
Conversion Time f
c
=
640 kHz, (
Figure 5
) (Note 7) 90 100 116 µs
f
c
Clock Frequency 10 640 1280 kHz
t
EOC
EOC Delay Time (
Figure 5
) 0 8+2 µS Clock
Periods
C
IN
Input Capacitance At Control Inputs 10 15 pF
C
OUT
TRI-STATE Output At TRI-STATE Outputs 10 15 pF
Capacitance
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless othewise specified.
Note 3: A zener diode exists, internally, from V
CC
to GND and has a typical breakdown voltage of 7 V
DC
.
Note 4: Two on-chip diodesare tied to each analoginput which will forward conductfor analog inputvoltages onediode drop belowground or one diode dropgreater
than the V
CC
n supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog V
IN
does not exceed the supply voltage by more
than 100 mV, the output code will be correct. To achieve an absolute 0V
DC
to 5V
DC
input voltage range will therefore require a minimum supply voltage of 4.900 V
DC
over temperature variations, initial tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. See
Figure 3
. None of theseA/Ds requires a zero or full-scale adjust. How-
ever, if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages
can be adjusted to achieve this. See
Figure 13
.
Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has little
temperature dependence (
Figure 6
). See paragraph 4.0.
Note 7: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 8: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
ADC0808/ADC0809
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