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器件3D模型￥ 12.452
ADC0809CCN 产品手册 - National Semiconductor（美国国家半导体）
制造商:
National Semiconductor（美国国家半导体）
分类:
AD转换器
封装:
PDIP-28
描述:
ADC0809CCN
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3D模型
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ADC0809CCN数据手册
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Functional Description
Multiplexer. The device contains an 8-channel single-ended
analog signal multiplexer. A particular input channel is se-
lected by usingthe address decoder.
Table 1
shows the input
states for the address lines to select any channel. The ad-
dress is latched into the decoderon the low-to-high transition
of the address latch enable signal.
TABLE 1.
SELECTED ADDRESS LINE
ANALOG
CHANNEL
CBA
IN0 L L L
IN1 L L H
IN2 L H L
IN3 L H H
IN4 H L L
IN5 H L H
IN6 H H L
IN7 H H H
CONVERTER CHARACTERISTICS
The Converter
The heart of this single chip data acquisition system is its
8-bit analog-to-digital converter. The converteris designed to
give fast, accurate, and repeatable conversions over a wide
range of temperatures. The converter is partitioned into 3
major sections: the 256R ladder network, the successive ap-
proximation register, and the comparator. The converter’s
digital outputs are positive true.
The 256R ladder network approach (
Figure 1
) was chosen
over the conventional R/2R ladder because of its inherent
monotonicity, which guarantees no missing digital codes.
Monotonicity is particularlyimportant in closed loop feedback
control systems.Anon-monotonic relationship can cause os-
cillations that will be catastrophicfor the system.Additionally,
the 256R network does not cause load variations on the ref-
erence voltage.
The bottom resistor and the top resistor of the ladder net-
work in
Figure 1
are not the same value as the remainder of
the network. The difference in these resistors causes the
output characteristic to be symmetrical with the zero and
full-scale points of the transfer curve. The first output transi-
tion occurs when the analog signal has reached +
1
⁄
2
LSB
and succeeding outputtransitions occur every 1 LSB later up
to full-scale.
The successive approximation register (SAR) performs 8 it-
erations to approximate the input voltage. For any SAR type
converter, n-iterations are required for an n-bit converter.
Figure 2
shows a typical example of a 3-bit converter. In the
ADC0808, ADC0809, the approximation technique is ex-
tended to 8 bits using the 256R network.
The A/D converter’s successive approximation register
(SAR) is reset on the positive edge of the start conversion
(SC) pulse. The conversion is begun on the falling edge of
the start conversion pulse. Aconversion in process will be in-
terrupted by receipt of a new start conversion pulse. Con-
tinuous conversion may be accomplished by tying the
end-of-conversion (EOC) output to the SC input. If used in
this mode, an external start conversion pulse should be ap-
plied after power up. End-of-conversion will go low between
0 and 8 clock pulses after the rising edge of start conversion.
The most important section of the A/D converter is the com-
parator. It is this section which is responsible for the ultimate
accuracy of the entire converter. It is also the comparator
drift which has the greatest influence on the repeatability of
the device. A chopper-stabilized comparator provides the
most effective method of satisfying all the converter require-
ments.
The chopper-stabilized comparator converts the DC input
signal into an AC signal. This signal is then fed through a
high gain AC amplifier and has the DC level restored. This
technique limits the drift component of the amplifier since the
drift is a DC component which is not passed by the AC am-
plifier. This makes the entire A/D converter extremely insen-
sitive to temperature, long term drift and input offset errors.
Figure 4
shows a typical error curve for the ADC0808 as
measured using the procedures outlined in AN-179.
ADC0808/ADC0809
www.national.com5
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