Datasheet 搜索 > DSP数字信号处理器 > ADI（亚德诺） > ADSP-BF561SBBZ600 数据手册 > ADSP-BF561SBBZ600 其他数据使用手册 1/64 页
器件3D模型￥ 39.089
ADSP-BF561SBBZ600 其他数据使用手册 - ADI（亚德诺）
制造商:
ADI（亚德诺）
分类:
DSP数字信号处理器
封装:
BGA-297
描述:
Blackfin嵌入式对称多处理器 Blackfin Embedded Symmetric Multiprocessor
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P10P17P18P19Hot
原理图在P1
封装尺寸在P22P61
型号编码规则在P20P22P63
功能描述在P3
技术参数、封装参数在P1P20P22P23P43
电气规格在P21
型号编号列表在P63
导航目录
ADSP-BF561SBBZ600数据手册
Page:
of 64 Go
若手册格式错乱，请下载阅览PDF原文件
GE
TOR
IRQ CONTROL/
WATCHDOG
TIMER
Blackfin Embedded
Symmetric Multiprocessor
FEATURES
Dual symmetric 600 MHz high performance Blackfin cores
328K bytes of on-chip memory
(see Memory Architecture on Page 4)
Each Blackfin core includes
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of pro-
gramming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages, (see Operating Conditions
on Page 20)
256-ball CSP_BGA (2 sizes) and 297-ball PBGA
package options
PERIPHERALS
Dual 12-channel DMA controllers
(supporting 24 peripheral DMAs)
2 memory-to-memory DMAs
VOLTA
REGULA
EXTERNAL PORT
FLASH/SDRAM CONTROL
32
16
32
16
BOOT ROM
PAB
EAB
DAB
DAB
PPI0
JTAG TEST
EMULATION
GPIO
SPI
SPORT0
TIMERS
SPORT1
IMDMA
CONTROLLER
B
CORE SYSTEM/BUS INTERFACE
B
DEB
UART
IrDA
DMA
CONTROLLER1
DMA
CONTROLLER2
PPI1
IRQ CONTROL/
WATCHDOG
TIMER
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
L2 SRAM
128K BYTES
ADSP-BF561
2 internal memory-to-memory DMAs and 1 internal memory
DMA controller
12 general-purpose 32-bit timers/counters with PWM
capability
SPI-compatible port
UART with support for IrDA
Dual watchdog timers
Dual 32-bit core timers
48 programmable flags (GPIO)
On-chip phase-locked loop capable of 0.5× to 64× frequency
multiplication
2 parallel input/output peripheral interface units supporting
ITU-R 656 video and glueless interface to analog front end
ADCs
2 dual channel, full duplex synchronous serial ports support-
ing eight stereo I
2
S channels
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
Tel: 781.329.4700 www.analog.com
registered trademarks are the property of their respective owners.
Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
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