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AT24C08C-SSHM-T
器件3D模型
0.603
导航目录
  • 引脚图在P5
  • 原理图在P4
  • 封装尺寸在P17P18P19
  • 型号编码规则在P15
  • 标记信息在P16P19
  • 功能描述在P3
  • 技术参数、封装参数在P12
  • 电气规格在P12
AT24C08C-SSHM-T数据手册
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GT24C08A
Giantec Semiconductor, Inc. www.giantec-semi.com
C2 3/21
1. Features
Two-Wire Serial Interface, I
2
C
TM
Compatible
Bi-directional data transfer protocol
Wide-voltage Operation
V
CC
= 1.7V to 5.5V
Speed: 400 KHz (1.7V) and 1 MHz (2.5V~5.5V)
Standby current (max.): 1 A, 1.7V
Operating current (max.): 2 mA, 5.5V
Hardware Data Protection
Write Protect Pin
Sequential & Random Read Features
Memory organization: 8Kb (1,024 x 8)
Page Size: 16 bytes
Page write mode
Partial page writes allowed
Self timed write cycle: 5 ms (max.)
Noise immunity on inputs, besides Schmitt trigger
High-reliability
Endurance: 1 million cycles
Data retention: 100 years
Industrial grade
Packages: SOIC, TSSOP, UDFN and MSOP
Lead-free, RoHS, Halogen free, Green
2. General Description
The GT24C08A is an industrial standard electrically
erasable programmable read only memory (EEPROM)
device that utilizes the industrial standard 2-wire interface
for communications. The GT24C08A contains a memory
array of 8K bits (1,024x8), which is organized in 16-byte per
page.
The EEPROM operates in a wide voltage range from 1.7V
to 5.5V, which fits most application. The product provides
low-power operations and low standby current. The device
is offered in Lead-free, RoHS, halogen free or Green
package. The available package types are 8-pin SOIC,
TSSOP, UDFN and MSOP.
The GT24C08A is compatible to the standard 2-wire bus
protocol. The simple bus consists of Serial Clock (SCL) and
Serial Data (SDA) signals. Utilizing such bus protocol, a
Master device, such as a microcontroller, can usually
control one or more Slave devices, alike this GT24C08A.
The bit stream over the SDA line includes a series of bytes,
which identifies a particular Slave device, an instruction, an
address within that Slave device, and a series of data, if
appropriate. The GT24C08A also has a Write Protect
function via WP pin to cease from overwriting the data
stored inside the memory array.
In order to refrain the state machine entering into a wrong
state during power-up sequence or a power toggle off-on
condition, a power on reset circuit is embedded. During
power-up, the device does not respond to any instructions
until the supply voltage (V
CC
) has reached an acceptable
stable level above the reset threshold voltage. Once V
CC
passes the power on reset threshold, the device is reset
and enters into the Standby mode. This would also avoid
any inadvertent Write operations during power-up stage.
During power-down process, the device will enter into
standby mode, once V
CC
drops below the power on reset
threshold voltage. In addition, the device will be in standby
mode after receiving the Stop command, provided that no
internal write operation is in progress. Nevertheless, it is not
recommended to send an command until the V
CC
reaches
its operating level.

AT24C08C-SSHM-T 数据手册

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24 页 / 0.8 MByte
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69 页 / 0.53 MByte
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21 页 / 0.46 MByte
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3 页 / 0.16 MByte

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