Datasheet 搜索 > 微控制器 > ATMEL（爱特美尔） > AT80C51RD2-SLRUM 数据手册 > AT80C51RD2-SLRUM 其他数据使用手册 1/4 页
器件3D模型￥ 11.17
AT80C51RD2-SLRUM 其他数据使用手册 - ATMEL（爱特美尔）
制造商:
ATMEL（爱特美尔）
分类:
微控制器
封装:
PLCC-44
描述:
80C51 系列 40 MHz 5.5 V 1 kB SRAM 高性能 8位 微控制器 - PLCC-44
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
功能描述在P1
导航目录
AT80C51RD2-SLRUM数据手册
Page:
of 4 Go
若手册格式错乱，请下载阅览PDF原文件
Active Errata List
•
During UART Reception, Clearing REN May Generate Unexpected IT
•
SPI Interface - Transmission on Master Mode
•
SPI Interface - SPI SS pin Limitation on Master/Slave
•
SPI - SPI Slave Responding in a Multislave Configuration When Not Selected by the
Master and its SPDAT Register Loaded
•
SPI - SPI Slave Not Responding When Selected and Not Loaded
•
ALE Disabled Toggles During Internal MOVX
•
Timer 2 - Baud Rate Generator - No IT When TF2 is Set by Software
•
Timer 2 - Baud Rate Generator - Long Start Time
•
SPI Slave Mode/Data Corrupted
•
32 kHz Oscillator for AT83C51IC2/T80C51ID2 Needs External Feed Back Resistor
•
RB8 Lost With JBC on SCON
•
C51 Core – Bad Exit of Power-down in X2 Mode
Errata History
Errata Descriptions
1. During UART Reception, Clearing REN May Generate Unexpected IT
During UART reception, if the REN bit is cleared between a start bit detection and
the end of reception, the UART will not discard the data (RI is set).
Workaround
Test REN at the beginning of Interrupt routine just after CLR RI, and run the Inter-
rupt routine code only if REN is set.
2. SPI Interface - Transmission on Master Mode
A 9th bit is transmitted by the interface when the clock rate is set on divide by 2
mode and a positive polarity is selected; the SPR2, SPR1, SPR0 bits are cleared
(000) and CPOL = 1 on the SPCON register.
Workaround
Set the clock rate divide by 4 and X2 mode.
3. SPI Interface - SPI SS pin Limitation on Master/Slave
The SS pin of the SPI does not return to an I/O when a One-to-One Master/Slave
intercommunication is performed.
Workaround
No
4. SPI - SPI Slave Responding in a Multislave Configuration When Not
Selected by the Master and its SPDAT Register Loaded
In a multislave configuration, if the master is sending the Sck and the Tx data to all
the slaves, and only one slave is selected, the non-selected slaves respond and
generate the end of the transmission interruption (SPIF) if their SPDAT registers
are loaded before the transmission.
Workaround
No
Rev Lot Number 1st Prod. Trouble List
A above 00395 Nov 2001 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
4242B–8051–03/08
80C51 MCUs
AT83C51RB2
AT83C51RC2
AT83C51IC2
AT80C51ID2
AT80C51RD2
Errata Sheet
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
