Datasheet 搜索 > 微控制器 > ATMEL（爱特美尔） > AT91SAM7X128C-AU 数据手册 > AT91SAM7X128C-AU 其他数据使用手册 2/662 页
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AT91SAM7X128C-AU 其他数据使用手册 - ATMEL（爱特美尔）
制造商:
ATMEL（爱特美尔）
分类:
微控制器
封装:
LQFP-100
描述:
SMART SAM7X/XC ARM® 7 微处理器Atmel® SMART SAM7X/XC ARM7TDMI® 闪存微控制器 (MCU) 具有功率和灵活性，提供用于全面联网、实时嵌入式系统。 它们具有嵌入式高速闪存和 SRAM，以及包含 10/100 以太网 MAC、USB 2.0 和具有无可匹敌数据率的 CAN 控制器的扩展外围设备套件。### ARM 微控制器，Atmel
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P46P144P196P245P270P338P464P544Hot
典型应用电路图在P45P315P349P431
原理图在P5P11P12P23P24P26P27P44P55P69P75P82
封装尺寸在P9P10P602P603P604P648P652
型号编码规则在P606P646P648P652P655
标记信息在P607P610P618P626P634P642P654
封装信息在P604
功能描述在P46P56P69P76P83P90P99P134P146P221P247P271
技术参数、封装参数在P654
应用领域在P144
电气规格在P9P10P56P588P590P602P608P613P621P628P637P642
导航目录
AT91SAM7X128C-AU数据手册
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2
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
Features
Incorporates the ARM7TDMI ARM Thumb
®
Processor
High-performance 32-bit RISC Architecture
High-density 16-bit Instruction Set
Leader in MIPS/Watt
EmbeddedICE
™
In-circuit Emulation, Debug Communication Channel Support
Internal High-speed Flash
512 Kbytes (SAM7X512) Organized in Two Banks of 1024 Pages of
256 Bytes (Dual Plane)
256 Kbytes (SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane)
128 Kbytes (SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane)
Single Cycle Access at Up to 30 MHz in Worst Case Conditions
Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
Page Programming Time: 6 ms, Including Page Auto-erase,
Full Erase Time: 15 ms
10,000 Write Cycles, 10-year Data Retention Capability,
Sector Lock Capabilities, Flash Security Bit
Fast Flash Programming Interface for High Volume Production
Internal High-speed SRAM, Single-cycle Access at Maximum Speed
128 Kbytes (SAM7X512)
64 Kbytes (SAM7X256)
32 Kbytes (SAM7X128)
Memory Controller (MC)
Embedded Flash Controller, Abort Status and Misalignment Detection
Reset Controller (RSTC)
Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout Detector
Provides External Reset Signal Shaping and Reset Source Status
Clock Generator (CKGR)
Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
Power Management Controller (PMC)
Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode
Four Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention
Mode for General Purpose 2-wire UART Serial Communication
Periodic Interval Timer (PIT)
20-bit Programmable Counter plus 12-bit Interval Counter
Windowed Watchdog (WDT)
12-bit key-protected Programmable Counter
Provides Reset or Interrupt Signals to the System
Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
Real-time Timer (RTT)
32-bit Free-running Counter with Alarm
Runs Off the Internal RC Oscillator
Two Parallel Input/Output Controllers (PIO)
Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
Input Change Interrupt Capability on Each I/O Line
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