Datasheet 搜索 > 8位微控制器 > ATMEL（爱特美尔） > ATMEGA128-16AU 数据手册 > ATMEGA128-16AU 其他数据使用手册 6/386 页
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ATMEGA128-16AU 其他数据使用手册 - ATMEL（爱特美尔）
制造商:
ATMEL（爱特美尔）
分类:
8位微控制器
封装:
TQFP-64
描述:
ATMEL ATMEGA128-16AU 微控制器, 8位, 低功率高性能, ATmega, 16 MHz, 128 KB, 4 KB, 64 引脚, TQFP
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P2P5P67P92P111P145Hot
原理图在P3P9P65P92P93P95P96P112P117P118P120P122
封装尺寸在P369P370
型号编码规则在P368P374P375P376P378
封装信息在P368P369P376
应用领域在P32P33P49P60P63P273P276P284P286P287
电气规格在P89P375
导航目录
ATMEGA128-16AU数据手册
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6
2467X–AVR–06/11
ATmega128
Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the Atmel
®
AVR
®
ATmega128 as listed on
page 76. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-
stated when a reset condition becomes active.
Note: The ATmega128 is by default shipped in ATmega103 compatibility mode. Thus, if the parts are not
programmed before they are put on the PCB, PORTC will be output during first power up, and until
the ATmega103 compatibility mode is disabled.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega128 as listed on page
77.
Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the ATmega128 as listed on page
80.
Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a Reset occurs.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
Port F also serves the functions of the JTAG interface.
In ATmega103 compatibility mode, Port F is an input Port only.
Port G (PG4..PG0) Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port G also serves the functions of various special features.
The port G pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
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