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器件3D模型￥ 47.505
ATMEGA1284P-MU 其他数据使用手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
8位微控制器
封装:
VQFN-44
描述:
8 位 PicoPower megaAVR 系列微控制器此系列 megaAVR 微控制器具有 picoPower 技术 — 非常适合节能。 它们提供大量程序和数据内存，性能高达 20 MIPS。 **picoPower megaAVR 微控制器的特色和优点** 片上闪存 SRAM 内部 EEPROM SPI TWI (I²C) USART、USB、CAN 和 LIN 接口 监控计时器 精密振荡器 GPIO 引脚 ADC DAC 内置温度传感器 内部参考电压 掉电检测器
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P11P15P99P115P146Hot
原理图在P14P18P263P666
型号编码规则在P644P645P646P647P648P649P650P651P667
封装信息在P652P653P655P656P657P658P659P660P661P662P663
应用领域在P48P58P70P74P277P281P295P296
电气规格在P80
导航目录
ATMEGA1284P-MU数据手册
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若手册格式错乱，请下载阅览PDF原文件
2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 1
Features
High-performance, low-power 8-bit AVR
®
Microcontroller
Advanced RISC architecture
131 powerful Instructions – most single-clock cycle execution
32 × 8 general purpose working registers
Fully static operation
Up to 20MIPS throughput at 20MHz
On-chip 2-cycle multiplier
High endurance non-volatile memory segments
16/32/64/128KBytes of In-System Self-programmable Flash program memory
512/1K/2K/4KBytes EEPROM
1/2/4/16KBytes Internal SRAM
Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
Data retention: 20 years at 85°C/ 100 years at 25°C
(1)
Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Programming Lock for Software Security
QTouch
®
Library Support
Capacitive touch buttons, sliders and wheels
QTouch and QMatrix™ acquisition
Up to 64 sense channels
JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the JTAG Standard
Extensive On-chip Debug Support
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
ATmega164A/PA/324A/PA/644A/PA/1284/P
megaAVR
®
Data Sheet
Introduction
The ATmega164A/PA/324A/PA/644A/PA/1284/P is a low power, CMOS 8-bit microcontrollers based on the
AVR
®
enhanced RISC architecture. The ATmega164A/PA/324A/PA/644A/PA/1284/P is a 40/49-pins device
ranging from 16 KB to 128 KB Flash, with 1 KB to 16 KB SRAM, 512 Bytes to 4 KB EEPROM. By executing
instructions in a single clock cycle, the devices achieve CPU throughput approaching one million instruc-
tions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption ver-
sus processing speed.
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