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ATXMEGA128A1U-CU 其他数据使用手册 - Microchip(微芯)
制造商:
Microchip(微芯)
分类:
8位微控制器
封装:
BGA-100
描述:
8位 MCU微控制单元, 低功率高性能, AVR ATxmega Family ATXmega A Series Microcontrollers, 32 MHz, 128 KB, 8 KB
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P9P39P63P65Hot
典型应用电路图在P8
原理图在P9P12P14P63
封装尺寸在P77P78P79
型号编码规则在P8P18
封装信息在P8P77
功能描述在P63
技术参数、封装参数在P80P103
应用领域在P8P17P18P23
电气规格在P19P80P218
导航目录
ATXMEGA128A1U-CU数据手册
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2018 Microchip Technology Inc. Data Sheet Complete DS40002058A-page 1
Features
High-performance, low-power AVR
®
XMEGA
®
8/16-bit Microcontroller
Nonvolatile program and data memories
64K - 128KBytes of in-system self-programmable flash
4K - 8KBytes boot section
2KBytes EEPROM
4K - 8KBytes internal SRAM
External bus interface for up to 16Mbytes SRAM
External bus interface for up to 128Mbit SDRAM
Peripheral features
Four-channel DMA controller
Eight-channel event system
Eight 16-bit timer/counters
Four timer/counters with 4 output compare or input capture channels
Four timer/counters with 2 output compare or input capture channels
High resolution extension on all timer/counters
Advanced waveform extension (AWeX) on two timer/counters
One USB device interface
USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
32 Endpoints with full configuration flexibility
Eight USARTs with IrDA support for one USART
Four two-wire interfaces with dual address match (I
2
C and SMBus compatible)
Four serial peripheral interfaces (SPIs)
AES and DES crypto engine
XMEGA
®
A1U Data Sheet
ATxmega128A1U/ATxmega64A1U
Introduction
The AVR
®
XMEGA
®
AU is a family of low power, high performance, and peripheral rich 8/16-bit microcon-
trollers based on the AVR enhanced RISC architecture. The XMEGA A1U is a 100-pins device ranging
from 64KB to 128KB Flash, with 4KB to 8KB SRAM, 2KB EEPROM and up to 8KB boot section. The
ATxmegaA1U devices operate at a maximum frequency of 32MHz. By executing instructions in a single
clock cycle, the devices achieve CPU throughput approaching one million instructions per second (MIPS)
per megahertz, allowing the system designer to optimize power consumption versus processing speed.
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