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C8051F411-GMR
器件3D模型
¥ 14.443
导航目录
  • 引脚图在P3P4P5
  • 典型应用电路图在P13
  • 型号编码规则在P2
  • 封装信息在P9P12
  • 技术参数、封装参数在P1
C8051F411-GMR数据手册
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Tested Single/Dual Battery, 0.9–3.6 V, 16 kB Flash,
SmaRTClock, 12/10-Bit ADC MCU Die in Wafer Form
C8051F912-GDI
Rev. 1.2 12/13 Copyright © 2013 by Silicon Laboratories C8051F912-GDI
Ultra-Low Power
-
160 µA/MHz in active mode (24.5 MHz clock)
- 2 µs wake-up time (two-cell mode)
- 10 nA sleep mode with memory retention
- 50 nA sleep mode with brownout detector
- 300 nA sleep mode with LFO
- 600 nA sleep mode with external crystal
Supply Voltage 0.9 to 3.6 V
-
One-cell mode supports 0.9 to 3.6 V operation
- Two-cell mode supports 1.8 to 3.6 V operation
- Built-in dc-dc converter with 1.8 to 3.3 V output for use
in one-cell mode
- Built-in LDO regulator allows a high analog supply volt-
age and low digital core voltage
- 2 built-in supply monitors (brownout detectors)
12 or 10-Bit Analog-to-Digital Converter
-
±1 LSB INL no missing codes (10-bit mode)
- Programmable throughput up to 300 ksps
(10-bit mode)
- 12-bit extended resolution mode provides ±1.5 LSB
INL at up to 75 ksps throughput
- 15 external inputs
- On-chip voltage reference
- On-chip PGA allows measuring voltages up to twice
the reference voltage
- 16-bit auto-averaging accumulator with burst mode
provides increased ADC resolution
- Data dependent windowed interrupt generator
- Built-in temperature sensor
Two Comparators
-
Programmable hysteresis and response time
- Configurable as wake-up or reset source
6-Bit Programmable Current Reference
-
Up to ± 500 A. Can be used as a bias or for generat-
ing a custom reference voltage
- PWM Enhanced Mode provides additional resolution
High-Speed 8051 C Core
-
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
-
768 bytes RAM
- 16 kB Flash; In-system programmable
Digital Peripherals
-
16 port I/O; All 5 V tolerant with high sink current and
programmable drive strength
- Hardware SMBus
TM
(I
2
C
TM
Compatible), 2 x SPI
TM
,
and UART serial ports available concurrently
- Four general purpose 16-bit counter/timers
- Programmable 16-bit counter/timer array with six cap-
ture/compare modules and watchdog timer
Clock Sources
-
Internal oscillators: 24.5 MHz, 2% accuracy supports
UART operation; 20 MHz low power oscillator requires
very little bias current
- External oscillator: Crystal, RC, C, or CMOS Clock
- SmaRTClock oscillator: 32 kHz crystal or internal LFO
- Can switch between clock sources on-the-fly; useful in
implementing various power saving modes
On-Chip Debug
-
On-chip debug circuitry facilitates full-speed, non-intru-
sive in-system debug (no emulator required)
- Provides 4 breakpoints, single stepping
- Inspect/modify memory and registers
- Complete development kit
Temperature range: –40 to +85
o
C
Full Technical Data Sheet
-
C8051F91x-C8051F90x
ANALOG
PERIPHERALS
16 kB
ISP FLASH
768 B SRAM
POR
DEBUG
CIRCUITRY
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
TEMP
SENSOR
DIGITAL I/O
24.5 MHz PRECISION
INTERNAL OSCILLATOR
HIGH-SPEED CONTROLLER CORE
A
M
U
X
CROSSBAR
VOLTAGE
COMPARATORS
+
WDT
UART
SMBus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 0
2 x SPI
IREF
Port 1
Port 2
+
VREG
20 MHz LOW POWER
INTERNAL OSCILLATOR
VREF
CRC
HARDWARE smaRTClockExternal Oscillator
12/10-bit
75/300 ksps
ADC

C8051F411-GMR 数据手册

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