Datasheet 搜索 > AD转换器 > Cirrus Logic（思睿逻辑） > CS5532-BS 数据手册 > CS5532-BS 其他数据使用手册 1/51 页
器件3D模型￥ 33.886
CS5532-BS 其他数据使用手册 - Cirrus Logic（思睿逻辑）
制造商:
Cirrus Logic（思睿逻辑）
分类:
AD转换器
封装:
SSOP
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
导航目录
CS5532-BS数据手册
Page:
of 51 Go
若手册格式错乱，请下载阅览PDF原文件
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
http://www.cirrus.com
CS5531/32/33/34
16-bit and 24-bit ADCs with Ultra-low-noise PGIA
Features
z Chopper-stabilized PGIA (Programmable
Gain Instrumentation Amplifier, 1x to 64x)
6 nV/√Hz @ 0.1 Hz (No 1/f noise) at 64x
500 pA Input Current with Gains >1
z
Delta-sigma Analog-to-digital Converter
Linearity Error: 0.0007% FS
Noise Free Resolution: Up to 23 bits
z
Two- or Four-channel Differential MUX
z Scalable Input Span via Calibration
±5 mV to differential ±2.5V
z
Scalable V
REF
Input: Up to Analog Supply
z Simple Three-wire Serial Interface
SPI™ and Microwire™ Compatible
Schmitt Trigger on Serial Clock (SCLK)
z
R/W Calibration Registers Per Channel
z Selectable Word Rates: 6.25 to 3,840 Sps
z Selectable 50 or 60 Hz Rejection
z Power Supply Configurations
VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
VA+ = +3 V; VA- = -3 V; VD+ = +3 V
General Description
The CS5531/32/33/34 are highly integrated ∆Σ Analog-
to-Digital Converters (ADCs) which use charge-balance
techniques to achieve 16-bit (CS5531/33) and 24-bit
(CS5532/34) performance. The ADCs are optimized for
measuring low-level unipolar or bipolar signals in weigh
scale, process control, scientific, and medical
applications.
To accommodate these applications, the ADCs
come as
either two-channel (CS5531/32) or four-channel
(CS5533/34) devices and include a very low noise chop-
per-stabilized instrumentation amplifier (6 nV/√Hz
@ 0.1
Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and
64×. These ADCs also include a fourth order ∆Σ modu-
lator followed by a digital filter
which provides twenty
selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30,
50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600,
1920, 3200, and 3840 Sps (MCLK = 4.9152 MHz).
To ease communication between the ADCs and a micro-
controller, the converters include a simple three-wire se-
rial interface which is SPI and Microwire compatible with
a Schmitt Trigger input on the serial clock (SCLK).
High dynamic range, programmable output rates, and
flexible power supply options makes these ADCs ideal
solutions for weigh scale and process control
applications.
ORDERING INFORMATION
See page 48
VA+ C1 C2 VREF+ VREF- VD+
DIFFERENTIAL
4
TH
ORDER
∆Σ
MODULATOR
PGIA
1,2,4,8,16
PROGRAMMABLE
SINC FIR FILTER
MUX
(CS5533/34
SHOWN)
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
AIN3-
AIN4+
AIN4-
SERIAL
INTERFACE
LATCH
CLOCK
GENERATOR
CALIBRATION
SRAM/CONTROL
LOGIC
DGND
CS
SDI
SDO
SCLK
OSC2OSC1A1A0/GUARDVA-
32,64
JUL ‘05
DS289F1
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
