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CS5532-BSZR 其他数据使用手册 - Cirrus Logic（思睿逻辑）
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Cirrus Logic（思睿逻辑）
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AD转换器
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CS5532-BSZR数据手册
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Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
http://www.cirrus.com
CS5532/34-BS
24-bit
∆Σ
ADCs with Ultra-low-noise PGIA
Features
Chopper-stabilized PGIA (Programmable
Gain Instrumentation Amplifier, 1x to 64x)
– 6 nV/√Hz @ 0.1 Hz (No 1/f noise) at 64x
– 1200 pA Input Current with Gains >1
Delta-sigma Analog-to-digital Converter
– Linearity Error: 0.0007% FS
– Noise-free Resolution: Up to 23 bits
Two- or Four-channel Differential MUX
Scalable Input Span via Calibration
– ±5 mV to differential ±2.5V
Scalable V
REF
Input: Up to Analog Supply
Simple Three-wire Serial Interface
– SPI™ and Microwire™ Compatible
– Schmitt Trigger on Serial Clock (SCLK)
R/W Calibration Registers Per Channel
Selectable Word Rates: 6.25 to 3,840 Sps
Selectable 50 or 60 Hz Rejection
Power Supply Configurations
– VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
– VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
– VA+ = +3 V; VA- = -3 V; VD+ = +3 V
General Description
The CS5532/34 are highly integrated ∆Σ Analog-to-Digi-
tal Converters (ADCs) which use charge-balance
techniques to achieve 24-bit performance. The ADCs
are optimized for measuring low-level unipolar or bipolar
signals in weigh scale, process control, scientific, and
medical applications.
To accommodate these applications, the ADCs
come as
either two-channel (CS5532) or four-channel (CS5534)
devices and include a very low-noise, chopper-stabilized
instrumentation amplifier (6 nV/√Hz
@ 0.1 Hz) with se-
lectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and 64×.
These ADCs also include a fourth-order ∆Σ modulator
followed by a digital filter
which provides twenty selectable
output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,
120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and
3840 Sps (MCLK = 4.9152 MHz).
To ease communication between the ADCs and a micro-
controller, the converters include a simple three-wire se-
rial interface which is SPI™ and Microwire™ compatible
with a Schmitt-trigger input on the serial clock (SCLK).
High dynamic range, programmable output rates, and
flexible power supply options makes these ADCs ideal
solutions for weigh scale and process control
applications.
ORDERING INFORMATION
See page 47
VA+ C1 C2 VREF+ VREF- VD+
DIFFERENTIAL
4
TH
ORDER
∆Σ
MODULATOR
PGIA
1,2,4,8,16
PROGRAMMABLE
SINC FIR FILTER
MUX
(CS5534
SHOWN)
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
AIN3-
AIN4+
AIN4-
SERIAL
INTERFACE
LATCH
CLOCK
GENERATOR
CALIBRATION
SRAM/CONTROL
LOGIC
DGND
CS
SDI
SDO
SCLK
OSC2OSC1A1A0/GUARDVA-
32,64
OCT ‘08
DS755F3
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