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器件3D模型￥ 41.356
CS8406-DZZR 其他数据使用手册 - Cirrus Logic（思睿逻辑）
制造商:
Cirrus Logic（思睿逻辑）
封装:
TSSOP-28
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P20P39P40P41P42P46P47P48P49Hot
典型应用电路图在P12P13P43
原理图在P58
封装尺寸在P51P52P53
型号编码规则在P1P2
封装信息在P2
功能描述在P2P14
技术参数、封装参数在P6P7
应用领域在P50P62
电气规格在P7
导航目录
CS8406-DZZR数据手册
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若手册格式错乱，请下载阅览PDF原文件
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
http://www.cirrus.com
192 kHz Digital Audio Interface Receiver
Features
! Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF-Compatible Receiver
! +3.3 V Analog Supply (VA)
! +3.3 V Digital Supply (VD)
! +3.3 V or +5.0 V Digital Interface Supply (VL)
! 8:2 S/PDIF Input MUX
! AES/SPDIF Input Pins Selectable in Hardware
Mode
! 3 General Purpose Outputs (GPO) Allow Signal
Routing
! Selectable Signal Routing to GPO Pins
! S/PDIF-to-TX Inputs Selectable in Hardware
Mode
! Flexible 3-wire Serial Digital Output Port
! 32 kHz to 192 kHz Sample Frequency Range
! Low-Jitter Clock Recovery
! Pin and Microcontroller Read Access to
Channel Status and User Data
! SPI™ or I²C Control Port Software Mode and
Stand-alone Hardware Mode
! Differential Cable Receiver
! On-Chip Channel Status Data Buffer Memories
! Auto-Detection of Compressed Audio Input
Streams
! Decodes CD Q Sub-Code
! OMCK System Clock Mode
See Ordering Information on page 2.
Clock &
Data
Recovery
Misc.
Control
Serial
Audio
Output
Receiver
AES3
S/PDIF
Decoder
Control
Port &
Registers
RXN
RXP1
OLRCK
OSCLK
SDOUT
RST
SDA/
CDOUT
SCL/
CCLK
AD1/
CDIN
AD0/
CS
AGND FILT
VL
DGND
RMCK
RXP2
RXP3
RXP4
RXP5
RXP6
RXP7
8:2
MUX
OMCK
GPO0
GPO1
AD2/GPO2
RXP0
n:3
MUX
VDVA
TX Passthrough
Format
Detect
C & U bit
Data Buffer
De-emphasis
Filter
AUGUST '05
DS578F1
CS8416
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