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DRV8885EVM 其他数据使用手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
开发套件
描述:
TEXAS INSTRUMENTS DRV8885EVM 评估电路板, DRV8885, 步进电机驱动器
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P3P4P5P27Hot
典型应用电路图在P15P45P46
原理图在P13P23
封装尺寸在P54P56P57
标记信息在P54
封装信息在P54P55P56P57
技术参数、封装参数在P6
电气规格在P8P9
导航目录
DRV8885EVM数据手册
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4
DRV8308
ZHCSC39A –FEBRUARY 2014–REVISED OCTOBER 2014
www.ti.com.cn
Copyright © 2014, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O
(1)
DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS
NAME NUMBER
(2) In SPI mode, these terminals are inputs; in EEPROM mode, they are open-drain outputs.
(3) When using FG amp, this terminal is an analog input. If in TACH mode, this is a logic-level input.
FAULTn 17 OD
Fault indicator – active low when
overcurrent, overtemperature, or rotor
stall detected. Open-drain output.
FGOUT 16 OD
Outputs a TACH signal generated from
the FG amplifier or Hall sensors.
Open-drain output.
LOCKn 18 OD
Outputs a signal that indicates the
speed loop is locked. Open-drain
output.
RESET 23 I
Active high to reset all internal logic.
Internal pulldown resistor.
SERIAL INTERFACE
SCLK
(2)
11 I/OD Serial clock
SPI mode: Serial clock input. Data is clocked on rising edges.
Internal pulldown resistor.
EEPROM mode: Connect to EEPROM CLK. Open-drain
output requires external pullup.
SCS
(2)
12 I/OD Serial chip select
SPI mode: Active high enables serial interface operation.
Internal pulldown resistor.
EEPROM mode: Connect to EEPROM CS. Open-drain output
requires external pullup.
SDATAI 14 I Serial data input
SPI mode: Serial data input. Internal pulldown resistor.
EEPROM mode: Serial data input. Connect to EEPROM DO
terminal.
SDATAO 15 OD Serial data output
SPI mode: Serial data output. Open-drain output.
EEPROM mode: Connect to EEPROM DI. Open-drain output
requires external pullup.
SMODE 13 I Serial mode
SPI mode: leave open or connect to ground for SPI interface
mode.
EEPROM mode: Connect to logic high to for EEPROM mode.
POWER STAGE INTERFACE
ISEN 31 I Low-side current sense resistor Connect to low-side current sense resistor
U 33 I
Measures motor phase voltages for
V
FETOCP
Connect to motor windingsV 36 I
W 39 I
UHSG 32 O
High-side FET gate outputs Connect to high-side 1/2-H N-channel FET gateVHSG 35 O
WHSG 38 O
ULSG 34 O
Low-side FET gate outputs Connect to low-side 1/2-H N-channel FET gateVLSG 37 O
WLSG 40 O
HALL AND FG INTERFACE
FGFB 8 O FG amplifier feedback terminal Connect feedback network to FGIN–
FGINN_TACH 9 I
(3)
FG amplifier negative input or TACH
input
Connect to FG trace and filter components. When using a
TACH with FGSEL= 3, connect a logic-level TACH signal. If
unused, connect FGFB to FG–.
FGINP 10 I/O FG amplifier positive input
Connect to FG trace and filter components on the PCB (if
used).
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