Datasheet 搜索 > FPGA芯片 > Altera（阿尔特拉） > EP1C20F400C7 数据手册 > EP1C20F400C7 产品封装文件 3/470 页
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EP1C20F400C7 产品封装文件 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
BGA-400
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P190P411P428Hot
典型应用电路图在P28P30P32
原理图在P28P100P189P217P229P259
封装尺寸在P12P449P451P452P453P454P455P456P457P458P459P460
型号编码规则在P11P181P453P455P457P459P461P463P465P467
功能描述在P27
技术参数、封装参数在P11P77P92P97P98P100P105P107P109P111P113P115
应用领域在P119P120P121P122P181P331P333P445
电气规格在P298P319P329P331P333
导航目录
EP1C20F400C7数据手册
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Altera Corporation iii
Contents
Chapter Revision Dates ........................................................................... xi
About This Handbook ............................................................................ xiii
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiii
Section I. Cyclone II Device Family Data Sheet
Revision History .................................................................................................................................... 1–1
Chapter 1. Introduction
Introduction ............................................................................................................................................ 1–1
Low-Cost Embedded Processing Solutions .................................................................................. 1–1
Low-Cost DSP Solutions ................................................................................................................. 1–1
Features ................................................................................................................................................... 1–2
Referenced Documents ......................................................................................................................... 1–9
Document Revision History ................................................................................................................. 1–9
Chapter 2. Cyclone II Architecture
Functional Description .......................................................................................................................... 2–1
Logic Elements ....................................................................................................................................... 2–2
LE Operating Modes ........................................................................................................................ 2–4
Logic Array Blocks ................................................................................................................................ 2–7
LAB Interconnects ............................................................................................................................ 2–8
LAB Control Signals ......................................................................................................................... 2–8
MultiTrack Interconnect ..................................................................................................................... 2–10
Row Interconnects .......................................................................................................................... 2–10
Column Interconnects .................................................................................................................... 2–12
Device Routing ............................................................................................................................... 2–15
Global Clock Network & Phase-Locked Loops ............................................................................... 2–16
Dedicated Clock Pins ..................................................................................................................... 2–20
Dual-Purpose Clock Pins .............................................................................................................. 2–20
Global Clock Network ................................................................................................................... 2–21
Global Clock Network Distribution ............................................................................................ 2–23
PLLs .................................................................................................................................................. 2–25
Embedded Memory ............................................................................................................................. 2–27
Memory Modes ............................................................................................................................... 2–30
Clock Modes .................................................................................................................................... 2–31
M4K Routing Interface .................................................................................................................. 2–31
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