EPM7128STC100-10F 产品封装文件 - Intel（英特尔）

© December 2011 Altera Corporation Package Information Datasheet for Mature Altera Devices

Package Information Datasheet for

Mature Altera Devices

This datasheet provides package and thermal resistance information for mature

Altera

®

devices. Package information includes the ordering code reference, package

acronym, leadframe material, lead finish (plating), JEDEC outline reference, lead

coplanarity, weight, moisture sensitivity level, and other special information. The

thermal resistance information includes device pin count, package name, and

not listed in this datasheet, refer to the Package and Thermal Resistance page of the

Altera website.

f For information about trays, tubes, and dry packs, refer to AN 71: Guidelines for

Handling J-Lead, QFP, and BGA Devices.

f RoHS-compliant devices are compatible with leaded-reflow temperatures. For more

information, refer to Altera’s RoHS-Compliant Devices literature page.

Device and Package Cross Reference

Table 2 through Table 22 lists the device, package type, and number of pins for each

Altera device listed in this datasheet. Altera devices listed in this datasheet are

available in the following packages:

■ Plastic J-Lead Chip Carrier (PLCC)

■ Plastic Quad Flat Pack (PQFP)

■ Power Quad Flat Pack (RQFP)

■ Thin Quad Flat Pack (TQFP)

■ Ultra FineLine BGA (UBGA)

DS-PKG-16.8