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FPF3042UCX
器件3D模型
3.712
导航目录
  • 引脚图在P4
  • 典型应用电路图在P2
  • 原理图在P3
  • 封装尺寸在P13
  • 型号编码规则在P1
  • 功能描述在P1P4
  • 技术参数、封装参数在P6P15
  • 应用领域在P1
  • 电气规格在P7
FPF3042UCX数据手册
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August 2014
© 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com
FPF3042 • Rev. 1.0.1
FPF3042 IntelliMAX 18 V-Rated, Dual-Input, Single-Output, Power-Source-Selector Switch
FPF3042
IntelliMAX 18 V-Rated, Dual-Input, Single-Output,
Power-Source-Selector Switch
Features
Dual-Input, Single-Output Load Switch (DISO)
Input Supply Operating Range:
- 4.0 V~12.4 V at V
IN
- 4.0 V~12.4 V at V
BUS
Typical R
ON
:
- 95 mΩ at V
IN
=5 V
- 70 mΩ at V
BUS
=5 V
Bidirectional Switch for V
IN
and V
BUS
Slew Rate Controlled:
- 50 µs at V
IN
for < 4.7 µF C
OUT
- 90 µs at V
BUS
for < 4.7 µF C
OUT
Maximum I
SW
: 2.7 A per Channel
Break-Before-Make Transition
Under-Voltage Lockout (UVLO)
Over-Voltage Lockout (OVLO)
Thermal Shutdown
Logic CMOS IO Meets JESD76 Standard for GPIO
Interface and Related Power Supply Requirements
ESD Protected:
- Human Body Model: >3 kV
- Charged Device Model: >1.5 kV
- IEC 61000-4-2 Air Discharge: >15 kV
- IEC61000-4-2 Contact Discharge: >8 kV
Description
The FPF3042 is an 18 V-rated Dual-Input Single-Output
(DISO) load switch consisting of two channels of slew-
rate-controlled, low-on-resistance, N-channel MOSFET
switches with protection features. The slew-rate-
controlled turn-on characteristic prevents inrush current
and the resulting excessive voltage droop on the input
power rails. The input voltage range operates from 4.0 V
to 12.4 V at both V
BUS
and V
IN
to align with the needs of
high-voltage portable device power rails.
Both V
IN
and V
BUS
have the over-voltage protection of
14 V (typical) to avoid damage to the system.
V
IN
and V
BUS
bidirectional switching allows reverse
current from V
OUT
to V
IN
or V
BUS
for On-The-Go, (OTG)
Mode. The switching is controlled by logic input EN and
V
IN_SEL
is capable of interfacing directly with low-voltage
control signal General-Purpose Input / Output (GPIO).
FPF3042 is available in 1.76 mm x 1.96 mm Wafer-
Level Chip-Scale Package (WLCSP), 16-bump, 0.4 mm
pitch.
Applications
Input Power-Selection Block Supporting USB and
Wireless Charging
Smart Phone / Tablet PC
Ordering Information
Part Number
Top
Mark
Channel
Typical R
ON
per
Channel at 5 V
IN
Rise Time (t
R
)
Package
FPF3042UCX
TR
DISO
95 for V
IN
50 µs for V
IN
16-Bump, 1.76 mm x 1.96 mm,
Wafer-Level Chip-Scale Package
(WLCSP), 0.4 mm Pitch
70 for V
BUS
90 µs for V
BUS

FPF3042UCX 数据手册

Fairchild(飞兆/仙童)
15 页 / 1.35 MByte

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