Datasheet 搜索 > 微控制器 > NXP（恩智浦） > LPC11C24FBD48/301, 数据手册 > LPC11C24FBD48/301, 其他数据使用手册 1/70 页
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LPC11C24FBD48/301, 其他数据使用手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微控制器
封装:
LQFP-48
描述:
NXP LPC11C24FBD48/301, 微控制器, 32位, 低功率, ARM 皮质-M0, 50 MHz, 32 KB, 8 KB, 48 引脚, LQFP
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P5P6P7P8P9P10P11P12P13P14Hot
原理图在P4
封装尺寸在P56P57P58P59P60
型号编码规则在P3
焊接温度在P61P62P63P64P65
功能描述在P1P14
技术参数、封装参数在P68
应用领域在P3P68
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LPC11C24FBD48/301,数据手册
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1. General description
The LPC11U2x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction
set and memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11U2x operate at CPU frequencies of up to 50 MHz.
Equipped with a highly flexible and configurable Full-Speed USB 2.0 device controller, the
LPC11U2x brings unparalleled design flexibility and seamless integration to today’s
demanding connectivity solutions.
The peripheral complement of the LPC11U2x includes up to 32 kB of flash memory, up to
10 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I
2
C-bus interface,
one RS-485/EIA-485 USART with support for synchronous mode and smart card
interface, two SSP interfaces, four general-purpose counter/timers, a 10-bit ADC
(Analog-to-Digital Converter), and up to 54 general-purpose I/O pins.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Non-Maskable Interrupt (NMI) input selectable from several input sources.
System tick timer.
Memory:
Up to 32 kB on-chip flash program memory.
Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.
Up to 10 kB SRAM data memory.
16 kB boot ROM.
In-System Programming (ISP) and In-Application Programming (IAP) for flash and
EEPROM via on-chip bootloader software.
ROM-based USB drivers. Flash updates via USB supported.
ROM-based 32-bit integer division routines.
Debug options:
Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan
Description Language).
Serial Wire Debug.
LPC11U2x
32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up
to 10 kB SRAM and 4 kB EEPROM; USB device; USART
Rev. 2 — 13 January 2012 Product data sheet
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