Datasheet 搜索 > 32位控制器 > NXP（恩智浦） > LPC1343FHN33 数据手册 > LPC1343FHN33 其他数据使用手册 1/103 页
器件3D模型￥ 8.936
LPC1343FHN33 其他数据使用手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
32位控制器
封装:
HVQFN
描述:
NXP LPC1343FHN33 微控制器, 32位, ARM 皮质-M3, 72 MHz, 32 KB, 8 KB, 33 引脚, HVQFN
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P9P10P16Hot
原理图在P7
封装尺寸在P85P86P87P88P89P90P91
型号编码规则在P3P4P5
焊接温度在P92P93P94P95P96
功能描述在P1P39
技术参数、封装参数在P100
应用领域在P3P100
导航目录
LPC1343FHN33数据手册
Page:
of 103 Go
若手册格式错乱，请下载阅览PDF原文件
1. General description
The LPC1110/11/12/13/14/15 are a ARM Cortex-M0 based, low-cost 32-bit MCU family,
designed for 8/16-bit microcontroller applications, offering performance, low power, simple
instruction set and memory addressing together with reduced code size compared to
existing 8/16-bit architectures.
The LPC1110/11/12/13/14/15 operate at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC1110/11/12/13/14/15 includes up to 64 kB of flash
memory, up to 8 kB of data memory, one Fast-mode Plus I
2
C-bus interface, one
RS-485/EIA-485 UART, up to two SPI interfaces with SSP features, four general purpose
counter/timers, a 10-bit ADC, and up to 42 general purpose I/O pins.
Remark: The LPC111x series consists of the LPC1100 series (parts
LPC111x/101/201/301), LPC1100L series (parts LPC111x/002/102/202/302), and the
LPC1100XL series (parts LPC111x/103/203/303/323/333). The LPC1100L and
LPC1100XL series include the power profiles, a windowed watchdog timer, and a
configurable open-drain mode.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Non-Maskable Interrupt (NMI) input selectable from several input sources
(LPC1100XL series only).
Serial Wire Debug.
System tick timer.
Memory:
64 kB (LPC1115), 56 kB (LPC1114/333), 48 kB (LPC1114/323), 32 kB
(LPC1114/102/201/202/203/301/302/303), 24 kB (LPC1113), 16 kB (LPC1112),
8 kB (LPC1111),or 4 kB (LPC1110) on-chip flash programming memory.
256 byte page erase function (LPC1100XL series only)
8 kB, 4 kB, 2 kB, or 1 kB SRAM.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
Digital peripherals:
Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors. In addition, a configurable open-drain mode is supported on the
LPC1100L and LPC1100XL series.
LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller; up to 64 kB flash and
8 kB SRAM
Rev. 7 — 1 March 2012 Product data sheet
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
