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MAX9286S32V234 产品设计图 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
开发套件
封装:
NAY-000
描述:
扩展板, MAX9286四GMSL解串器, 1.5 MBPS, 用于SBC-S32V234
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MAX9286S32V234数据手册
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S32V234
S32V234 Data Sheet
Features
• ARM® Cortex®-A53, 64-bit CPU
– Up to 1000 MHz Quad ARM Cortex-A53
– 32 KB/32 KB I-/D- L1 Cache
– NEON MPE co-processor
– Dual precision FPU
– 2 clusters with 2 CPUs and 256 KB L2 cache each
– Memory Management Unit
– GIC Interrupt Controller
– ECC/parity error support for its memories
– Generic timers
– Fault encapsulation by hardware for redundant
executed application software on multiple core
cluster
• ARM Cortex-M4, 32-bit CPU
– Up to 133 MHz
– 16 KB/16 KB I-/D- L1 Cache
– 32+32 KB tightly coupled memory (TCM)
– ECC/parity support for its memories
• Clocks
– Phase Locked Loops (PLLs)
– 1 external crystal oscillator (FXOSC)
– 1 FIRC oscillator
• System protection and power management features
– Flexible run modes to consume low power based on
application needs
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
– Power gating of unused A53 cores and GPU
– Low and high voltage warning and detect
– Hardware CRC module to support fast cyclic
redundancy checks (CRC)
– 120-bit unique chip identifier
– Hardware watchdog
– eDMA controller with 32 channels (with
DMAMUX)
– Extended Resource Domain Controller
• Safety concept
– ISO 26262, ASIL level target
– Measures to detect faults in memory and logic
– Measures to detect single point and latent faults
– Quantitative out of context analysis of functional
safety (FMEDA) tailored to application specifics
– Safety manual and FMEDA report available
• Security
– CSE with 16 KB of on-chip Secure RAM and ROM.
– ARM TrustZone (TZ) architecture support
– Boot from NOR flash with AES-128 (CTR)
– On-Chip One-Time Programmable element
Controller (OCOTP_CTRL) with on chip electrical
fuse array.
– System JTAG Controller (SJC)
• Debug functionality
– Standard JTAG and Compact JTAG
– 16-bit Trace port, Serial Wire Output port
• Timers
– General purpose timers (FTM)
– Two Periodic Interrupt Timer (PIT)
– IEEE 1588 Timers (part of Ethernet Subsystem)
• Analog
– 1x 12-bit 1.8 V SAR ADC with self-test
• Communications
– UART(w/ LIN2.1l)
– Serial peripheral interface (SPI)
– I2C blocks
– PCI express 2.0 with endpoint and root complex
support
– LFAST serial link
– 1 GBit Ethernet with PTP IEEE 1588
– FD-CAN
– FlexRay Dual Channel, Version 2.1 RevA
NXP Semiconductors
Document Number S32V234
Data Sheet: Product Preview
Rev. 3.1, 07/2017
This document contains information on a product under development. NXP
reserves the right to change or discontinue this product without notice.
Preliminary
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