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MC12080D 其他数据使用手册 - ON Semiconductor（安森美）
制造商:
ON Semiconductor（安森美）
分类:
时钟信号器件
封装:
SOIC-8
描述:
1.1 GHz的预分频器高频输入信号 1.1 GHz Prescaler High Frequency Input Signal
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MC12080D数据手册
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© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 7
1 Publication Order Number:
MC12080/D
MC12080
1.1 GHz Prescaler
Description
The MC12080 is a single modulus divide by 10, 20, 40, 80 prescaler
for low power frequency division of a 1.1 GHz high frequency input
signal. Divide ratio control inputs SW1, SW2 and SW3 select the
required divide ratio of ÷10, ÷20, ÷40, or ÷80.
An external load resistor is required to terminate the output. An
820 W resistor is recommended to achieve a 1.2 V
pp
output swing,
when dividing a 1.1 GHz input signal by the minimum divide by ratio
of 10, assuming a 8.0 pF load. Output current can be minimized
dependent on conditions such as output frequency, capacitive load
being driven, and output voltage swing required. Typical values for
load resistors are included in the V
out
specification for various divide
ratios at 1.1 GHz input frequency.
Features
• 1.1 GHz Toggle Frequency
• Supply Voltage 4.5 to 5.5 V
• Low Power 3.7 mA Typical at V
CC
= 5.0 V
• Operating Temperature Range of −40 to 85°C
• These Devices are Pb−Free and are RoHS Compliant
Table 1. MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage, Pin 2 V
CC
−0.5 to 7.0 Vdc
Operating Temperature Range T
A
−40 to 85 °C
Storage Temperature Range T
stg
−65 to 150 °C
Maximum Output Current, Pin 4 I
O
10 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
Table 2. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
> 1500 V
> 100 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0
@ 0.125 in
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
SOIC−8
D SUFFIX
CASE 751
PIN CONNECTIONS
MARKING
DIAGRAM
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
In
8
In
V
CC
SW1
Out
SW3
SW2
GND
7
6
5
1
2
3
4
(Top View)
http://onsemi.com
1
8
12080
ALYW
G
1
8
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
FUNCTION TABLE
L
SW1 Divide Ratio
80
SW3
LL
SW2
L40HL
L40
LH
L20
HH
H40
LL
H20
HL
H20
LH
H10HH
NOTE: SW1, SW2 and SW3: H = V
CC
, L = Open.
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