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MC14025BDR2G 其他数据使用手册 - ON Semiconductor（安森美）
制造商:
ON Semiconductor（安森美）
分类:
逻辑芯片
封装:
SOIC-14
描述:
ON SEMICONDUCTOR MC14025BDR2G 或非门, CMOS, 缓冲器ed输出, 3输入, 3V至18V, NSOIC-14
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引脚图在P2Hot
典型应用电路图在P2
原理图在P5
封装尺寸在P11P12P13P14
焊盘布局在P12P13
型号编码规则在P1P8P9P10P14
标记信息在P1
封装信息在P10
技术参数、封装参数在P10
电气规格在P3P7
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MC14025BDR2G数据手册
Page:
of 14 Go
若手册格式错乱，请下载阅览PDF原文件
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 6
1 Publication Order Number:
MC14001B/D
MC14001B Series
B−Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range.
• Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
• Pin−for−Pin Replacements for Corresponding CD4000 Series
B Suffix Devices
• Pb−Free Packages are Available
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Symbol Parameter Value Unit
V
DD
DC Supply Voltage Range −0.5 to +18.0 V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V
DD
+ 0.5 V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
± 10 mA
P
D
Power Dissipation, per Package
(Note 1)
500 mW
T
A
Ambient Temperature Range −55 to +125 °C
T
stg
Storage Temperature Range −65 to +150 °C
T
L
Lead Temperature
(8−Second Soldering)
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v (V
in
or V
out
) v V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
Device Description
DEVICE INFORMATION
MC14001B Quad 2−Input NOR Gate
MC14011B Quad 2−Input NAND Gate
MC14023B Triple 3−Input NAND Gate
MC14025B Triple 3−Input NOR Gate
MC14071B Quad 2−Input OR Gate
MARKING
DIAGRAMS
1
14
PDIP−14
P SUFFIX
CASE 646
MC140xxBCP
AWLYYWWG
SOIC−14
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
1
14
140xxBG
AWLYWW
14
0xxB
ALYWG
G
1
14
xx = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
SOEIAJ−14
F SUFFIX
CASE 965
1
14
MC140xxB
ALYWG
MC14073B Triple 3−Input AND Gate
MC14081B Quad 2−Input AND Gate
MC14082B Dual 4−Input AND Gate
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
(Note: Microdot may be in either location)
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