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MC14569BCP 其他数据使用手册 - ON Semiconductor（安森美）
制造商:
ON Semiconductor（安森美）
分类:
计数器
封装:
PDIP-16
描述:
可编程分频-N双4位二进制/ BCD减计数器 Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter
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引脚图在P2P5Hot
典型应用电路图在P10P11
原理图在P2
封装尺寸在P12P13
型号编码规则在P1P2P14
标记信息在P1
封装信息在P2
技术参数、封装参数在P2
应用领域在P1P11
电气规格在P3
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MC14569BCP数据手册
Page:
of 14 Go
若手册格式错乱，请下载阅览PDF原文件
Semiconductor Components Industries, LLC, 2005
February, 2005 − Rev. 5
1 Publication Order Number:
MC14569B/D
MC14569B
Programmable Divide−By−N
Dual 4−Bit Binary/BCD
Down Counter
The MC14569B is a programmable divide−by−N dual 4−bit binary
or BCD down counter constructed with MOS P−Channel and
N−Channel enhancement mode devices (complementary MOS) in a
monolithic structure.
This device has been designed for use with the MC14568B phase
comparator/counter in frequency synthesizers, phase−locked loops,
and other frequency division applications requiring low power
dissipation and/or high noise immunity.
Features
• Speed−up Circuitry for Zero Detection
• Each 4−Bit Counter Can Divide Independently in BCD or Binary Mode
• Can be Cascaded With MC14526B for Frequency Synthesizer
Applications
• All Outputs are Buffered
• Schmitt Triggered Clock Conditioning
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Symbol Parameter Value Unit
V
DD
DC Supply Voltage Range −0.5 to +18.0 V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V
DD
+ 0.5 V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±10 mA
P
D
Power Dissipation, per Package
(Note 1)
500 mW
T
A
Ambient Temperature Range −55 to +125 °C
T
stg
Storage Temperature Range −65 to +150 °C
T
L
Lead Temperature
(8−Second Soldering)
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
) V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
MC14569BCP
AWLYYWW
SOIC−16
DW SUFFIX
CASE 751G
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
16
1
14569B
AWLYYWW
16
1
TSSOP−16
DT SUFFIX
CASE 948F
14
569B
ALYW
1
16
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