Datasheet 搜索 > ON Semiconductor（安森美） > MC74ACT14 数据手册 > MC74ACT14 产品设计图 1/7 页
￥ 0
MC74ACT14 产品设计图 - ON Semiconductor（安森美）
制造商:
ON Semiconductor（安森美）
描述:
六反相施密特触发器 Hex Inverter Schmitt Trigger
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
型号编码规则在P7
技术参数、封装参数在P1P2
导航目录
MC74ACT14数据手册
Page:
of 7 Go
若手册格式错乱，请下载阅览PDF原文件
© Semiconductor Components Industries, LLC, 2006
September, 2006 − Rev. 0
1 Publication Order Number:
AND8277/D
AND8277/D
Ratings, Specifications and
Waveforms for FACT Data
Sheets
Specifying FACT Devices
Traditionally, when a semiconductor manufacturer
completed a new device for introduction, specifications were
based on the characterization of just a few parts. While these
specifications were appealing to the designer, they were
often too tight and, over time, the IC manufacturers had
difficulty producing devices to the original specs. This forced
the manufacturer to relax circuit specifications to reflect the
actual performance of the device.
As a result, designers were required to review system
designs to ensure the system would remain reliable with the
new specifications. Motorola realized and understood the
problems associated with characterizing devices too
aggressively.
To provide more realistic and manufacturable specs,
Motorola devised a systematic and thorough process to
generate specifications. Devices are selected from multiple
wafer lots to ensure process variations are taken into
account. In addition, the process parameters are measured
and compared to the known process limits.
This method of characterizing parts more accurately
represents the product across time, voltage, temperature
and process rather than portraying the fastest possible
device. FACT circuits are therefore guaranteed to be
manufacturable over time without the need to respecify
timing.
These specification guidelines allow designers to design
systems more efficiently since the devices used will behave
as documented. Unspecified guardbands no longer need to
be added by the designer to ensure system reliability.
Power Dissipation — Test Philosophy
In an effort to reduce confusion about measuring C
PD
, a
JEDEC standard test procedure (per JEDEC, Appendix E)
has been adopted which specifies the test setup for each
type of device. This allows a device to be exercised in a
consistent manner for the purpose of specification
comparison. All device measurements are made with V
CC
=
5 V at 25°C, with 3-state outputs both enabled and disabled.
Gates — Switch one input. Bias the remaining inputs such
that the output switches.
Latches — Switch the Enable and D inputs such that the
latch toggles.
Flip-Flops — Switch the clock pin while changing D (or bias
J and K) such that the output(s) change each clock cycle. For
parts with a common clock, exercise only one flip-flop.
Decoders — Switch one address pin which changes two
outputs.
Multiplexers — Switch one address pin with the
corresponding data inputs at opposite logic levels so that the
output switches.
Counters — Switch the clock pin with other inputs biased
such that the device counts.
Shift Registers — Switch the clock pin with other inputs
biased such that the device counts.
Transceivers — Switch one data input. For bidirectional
devices enable only one direction.
Parity Generator — Switch one input.
Priority Encoders — Switch the lowest priority input.
Load Capacitance — Each output which is switching should
be loaded with the standard 50 pF.
If the device is tested at a high enough frequency, the static
supply current can be ignored. Thus at 1 MHz, the following
formula can be used to calculate C
PD
:
C
PD
= I
CC
/(V
CC
) (1 × 10
6
) − Equivalent Load Capacitance
APPLICATION NOTE
http://onsemi.com
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
