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MC74HC573ADT 产品封装文件 - ON Semiconductor（安森美）
制造商:
ON Semiconductor（安森美）
分类:
锁存器
封装:
TSSOP-20
描述:
八路三态同相透明锁存器 Octal 3-State Noninverting Transparent Latch
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MC74HC573ADT数据手册
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© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 16
1 Publication Order Number:
MC74HC573A/D
MC74HC573A
Octal 3-State Noninverting
Transparent Latch
High−Performance Silicon−Gate CMOS
The MC74HC573A is identical in pinout to the LS573. The devices
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The HC573A is identical in function to the HC373A but has the data
inputs on the opposite side of the package from the outputs to facilitate
PC board layout.
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 218 FETs or 54.5 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
LATCH ENABLE
OUTPUT ENABLE
11
1
9
8
7
6
5
4
3
219
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PIN 20 = V
CC
PIN 10 = GND
NONINVERTING
OUTPUTS
LOGIC DIAGRAM
Design Criteria
*Equivalent to a two−input NAND gate.
Value Units
Internal Gate Count*
54.5 ea.
Internal Gate Progation Delay
1.5 ns
Internal Gate Power Dissipation
5.0 mW
Speed Power Product
0.0075 pJ
http://onsemi.com
1
20
MARKING DIAGRAMS
SOIC−20
DW SUFFIX
CASE 751D
74HC573A
AWLYYWWG
HC
573A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
20
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
SOIC−20 TSSOP−20
D4
D2
D1
D0
OUTPUT
ENABLE
GND
D7
D6
D5
D3 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q3
Q2
Q1
Q0
V
CC
LATCH
ENABLE
Q7
Q6
Q5
Q4
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
Output Latch
Enable Enable D Q
LHHH
LHLL
L L X No Change
HXXZ
X = Don’t Care
Z = High Impedance
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