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MC74HC74ADR2 其他数据使用手册 - ON Semiconductor（安森美）
制造商:
ON Semiconductor（安森美）
分类:
触发器
封装:
SOIC-14
描述:
双D触发器具有置位和复位高性能硅栅CMOS Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
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MC74HC74ADR2数据手册
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© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 14
1 Publication Order Number:
MC74HC74A/D
MC74HC74A
Dual D Flip-Flop with Set
and Reset
High−Performance Silicon−Gate CMOS
The MC74HC74A is identical in pinout to the LS74. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q
outputs are available from each flip−flop. The Set
and Reset inputs are asynchronous.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 128 FETs or 32 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
RESET 1
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
SET 2
1
2
3
4
13
12
11
10
5
6
9
8
Q1
Q1
Q2
Q2
PIN 14 = V
CC
PIN 7 = GND
LOGIC DIAGRAM
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MARKING DIAGRAMS
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
TSSOP−14
DT SUFFIX
CASE 948G
SOIC−14 NB
D SUFFIX
CASE 751A
HC74AG
AWLYWW
1
14
HC
74A
ALYWG
G
1
14
(Note: Microdot may be in either location)
TSSOP−14
SOIC−14 NB
PIN ASSIGNMENT
SET 1
CLOCK 1
DATA 1
RESET 1
11
12
13
14
8
9
105
4
3
2
1
7
6
SET 2
CLOCK 2
DATA 2
RESET 2
V
CC
Q2
Q2
GND
Q1
Q1
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