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MC9S12D64CFUE 产品描述及参数 - NXP(恩智浦)
制造商:
NXP(恩智浦)
分类:
微控制器
封装:
QFP-80
描述:
S12A/D 系列微控制器装置S12A/D 系列为 16 位微控制器装置 (MCU),也可为低成本系统连接单 8 位宽内存。 该集成 PLL 电路提供功耗和性能灵活性,以满足用户的操作要求。 S12A/D 微控制器装置包括以下标准芯片外围设备; HCS12 CPU 64 K 字节闪存 EEPROM 1 K 字节 EEPROM 4 K 字节 RAM 2 个异步串行通信接口 (SCI) 1 个串行外围接口 (SPI) 8 通道 IC/OC 增强型捕获计时器 2 个 8 通道 10 位模拟至数字转换器 (ADC) 8 通道脉冲宽度调制器 (PWM) 数字字节数据链接控制器 (BDLC) 29 个分离式数字 I/O 通道 20 个分离式数字 I/O 线路 可与 CAN 软件兼容的模块 Byteflight 模块 I2C 总线### S12 微控制器,FreescaleFreescale S12 微控制器是高性能的 16 位设备,用于汽车和工业应用。
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P5P6P7P8P9P10Hot
原理图在P3P4
封装尺寸在P35
型号编码规则在P35P36
功能描述在P35
技术参数、封装参数在P1P11P12P13P14P15P16P17P18P19P20P21
电气规格在P11P12P13P14P15P16P17P18P19P20P21P22
导航目录
MC9S12D64CFUE数据手册
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824D-02
MC9S08AC128
840B-01
917A-03
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08AC128
Rev. 4, 8/2011
© Freescale Semiconductor, Inc., 2007-2011. All rights reserved.
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
MC9S08AC128 8-Bit
Microcontroller Data Sheet
8-Bit HCS08 Central Processor Unit (CPU)
• 40-MHz HCS08 CPU (central processor unit)
• 20-MHz internal bus frequency
• HC08 instruction set with added BGND, CALL and
RTC instructions
• Memory Management Unit to support paged
memory.
• Linear Address Pointer to allow direct page data
accesses of the entire memory map
Development Support
• Background debugging system
• Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
• On-chip in-circuit emulator (ICE) Debug module
containing three comparators and nine trigger
modes. Eight deep FIFO for storing change-of-flow
addresses and event-only data. Supports both tag
and force breakpoints.
Memory Options
• Up to 128K FLASH — read/program/erase over full
operating voltage and temperature
• Up to 8K Random-access memory (RAM)
• Security circuitry to prevent unauthorized access to
RAM and FLASH contents
Clock Source Options
• Clock source options include crystal, resonator,
external clock, or internally generated clock with
precision NVM trimming using ICG module
System Protection
• Optional computer operating properly (COP) reset
with option to run from independent internal clock
source or bus clock
• CRC module to support fast cyclic redundancy
checks on system memory
• Low-voltage detection with reset or interrupt
• Illegal opcode detection with reset
• Master reset pin and power-on reset (POR)
Power-Saving Modes
• Wait plus two stops
Peripherals
• ADC — 16-channel, 10-bit resolution, 2.5 s
conversion time, automatic compare function,
temperature sensor, internal bandgap reference
channel
• SCIx — Two serial communications interface
modules supporting LIN 2.0 Protocol and SAE J2602
protocols; Full duplex non-return to zero (NRZ);
Master extended break generation; Slave extended
break detection; Wakeup on active edge
• SPIx — One full and one master-only serial
peripheral interface modules; Full-duplex or
single-wire bidirectional; Double-buffered transmit
and receive; Master or Slave mode; MSB-first or
LSB-first shifting
• IIC — Inter-integrated circuit bus module; Up to 100
kbps with maximum bus loading; Multi-master
operation; Programmable slave address; Interrupt
driven byte-by-byte data transfer; supports broadcast
mode and 10 bit addressing
• TPMx — One 2-channel and two 6-channel 16-bit
timer/pulse-width modulator (TPM) modules:
Selectable input capture, output compare, and
edge-aligned PWM capability on each channel. Each
timer module may be configured for buffered,
centered PWM (CPWM) on all channels
• KBI — 8-pin keyboard interrupt module
Input/Output
• Up to 70 general-purpose input/output pins
• Software selectable pullups on input port pins
• Software selectable drive strength and slew rate
control on ports when used as outputs
Package Options
• 80-pin low-profile quad flat package (LQFP)
• 64-pin quad flat package (QFP)
• 48-pin quad flat no-lead package (QFN)
• 44-pin low-profile quad flat package (LQFP)
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