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MCIMX6S5EVM10AD 其他数据使用手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
封装:
LFBGA-624
Pictures:
3D模型
符号图
焊盘图
引脚图
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原理图在P10
封装尺寸在P21P34P136P137P138P139P140P141P142P143P144P145
型号编码规则在P3P5
标记信息在P5
功能描述在P100
技术参数、封装参数在P19P23P24P25P82P85P86P87P91P105P106P107
应用领域在P2P3P4P5P6P7P8P9P10P11P12P13
电气规格在P23P24P25P26P27P28P29P30P31P32P33P34
型号编号列表在P3P4P9
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MCIMX6S5EVM10AD数据手册
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NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX6SDLCEC
Rev. 8, 09/2017
Package Information
Plastic Package
BGA Case 2240 21 x 21 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 3
© 2012-2017 NXP B.V.
MCIMX6SxDxxxxxB
MCIMX6SxDxxxxxC
MCIMX6SxDxxxxxD
MCIMX6UxDxxxxxB
MCIMX6UxDxxxxxC
MCIMX6UxDxxxxxD
MCIMX6SxExxxxxB
MCIMX6SxExxxxxC
MCIMX6SxExxxxxD
MCIMX6UxExxxxxB
MCIMX6UxExxxxxC
MCIMX6UxExxxxxD
1 Introduction
The i.MX 6Solo/6DualLite processors represent the
latest achievement in integrated multimedia-focused
products offering high performance processing with
lower cost, as well as optimization for low power
consumption.
The processors feature advanced implementation of
single/dual ARM
®
Cortex
®
-A9 core, which operates at
speeds of up to 1 GHz. They include 2D and 3D graphics
processors, 1080p video processing, and integrated
power management. Each processor provides a 32/64-bit
DDR3/DDR3L/LPDDR2-800 memory interface and a
number of other interfaces for connecting peripherals,
such as WLAN, Bluetooth
®
, GPS, hard drive, displays,
and camera sensors.
The i.MX 6Solo/6DualLite processors are specifically
useful for applications such as:
• Web and multimedia tablets
• Web and multimedia tablets
i.MX 6Solo/6DualLite
Applications Processors
for Consumer Products
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3 Updated Signal Naming Convention . . . . . . . . . . . .9
2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1 Special Signal Considerations . . . . . . . . . . . . . . . .21
3.2 Recommended Connections for Unused Analog
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .23
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . .23
4.2 Power Supplies Requirements and Restrictions. . .33
4.3 Integrated LDO Voltage Regulator Parameters . . .34
4.4 PLL’s Electrical Characteristics. . . . . . . . . . . . . . . .37
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . .38
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .39
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .45
4.8 Output Buffer Impedance Parameters . . . . . . . . . .49
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . .52
4.10 General-Purpose Media Interface (GPMI) Timing .64
4.11 External Peripheral Interface Parameters. . . . . . . .72
5 Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . .134
5.1 Boot Mode Configuration Pins . . . . . . . . . . . . . . .134
5.2 Boot Device Interface Allocation. . . . . . . . . . . . . .135
6 Package Information and Contact Assignments . . . . . .136
6.1 Updated Signal Naming Convention . . . . . . . . . .136
6.2 21x21 mm Package Information . . . . . . . . . . . . . .137
7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
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