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MIC5891BWM
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MIC5891BWM数据手册
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May 2006 5 MIC5891
MIC5891 Micrel, Inc.
Applications Information
Serial data present at the input is transferred into the shift
register on the rising edge of the CLOCK input pulse. Additional
CLOCK pulses shift data information towards the SERIAL
DATA OUTPUT. The serial data must appear at the input prior
to the rising edge of the CLOCK input waveform.
The 8 bits present in the shift register are transferred to the
respective latches when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
Truth Table
Serial Shift Register Contents Serial Latch Contents Output Content
Data Clock Data Strobe Output
Input Input I
1
I
2
I
3
I
N-1
I
N
Output Input I
1
I
2
I
3
I
N-1
I
n
Enable I
1
I
2
I
3
I
N-1
I
n
H H R
1
R
2
R
N-2
R
N-1
R
N-1
L L R
1
R
2
R
N-2
R
N-1
R
N-1
X R
1
R
2
R
3
R
N-1
R
N
R
N
X X X X X X L R
1
R
2
R
3
R
N-1
R
N
P
1
P
2
P
3
P
N-1
P
N
P
N
H P
1
P
2
P
3
P
N-1
P
N
L P
1
P
2
P
3
P
N-1
P
N
X X X X X H L L L L L
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
long as the STROBE is held high. Most applications where the
latching feature is not used (STROBE tied high) require the
OUTPUT ENABLE input to be high during serial data entry.
Outputs are active (controlled by the latch state) when the
OUTPUT ENABLE is low. All Outputs are low (disabled) when
the OUTPUT ENABLE is high. OUTPUT ENABLE does not
affect the data in the shift register or latch.

MIC5891BWM 数据手册

Micrel(迈瑞)
7 页 / 0.16 MByte
Micrel(迈瑞)
7 页 / 0.16 MByte

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