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MPC8347CVVAGDB 其他数据使用手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微处理器
封装:
TBGA-672
描述:
PowerPC系列 400MHz
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3D模型
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MPC8347CVVAGDB数据手册
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Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
vi Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
2.3.2 Processor Version Register (PVR)............................................................................. 2-21
2.3.3 BAT Registers............................................................................................................ 2-21
2.3.4 SDR1..........................................................................................................................2-24
2.3.5 Segment Registers...................................................................................................... 2-25
2.3.6 Data Address Register (DAR) ................................................................................... 2-26
2.3.7 SPRG0–SPRG3 ......................................................................................................... 2-26
2.3.8 DSISR........................................................................................................................2-27
2.3.9 Machine Status Save/Restore Register 0 (SRR0)...................................................... 2-27
2.3.10 Machine Status Save/Restore Register 1 (SRR1)...................................................... 2-28
2.3.11 Floating-Point Exception Cause Register (FPECR).................................................. 2-28
2.3.12 Time Base Facility (TB)—OEA................................................................................2-29
2.3.12.1 Writing to the Time Base....................................................................................... 2-29
2.3.13 Decrementer Register (DEC)..................................................................................... 2-29
2.3.13.1 Decrementer Operation.......................................................................................... 2-30
2.3.13.2 Writing and Reading the DEC............................................................................... 2-30
2.3.14 Data Address Breakpoint Register (DABR )............................................................. 2-30
2.3.15 External Access Register (EAR)................................................................................ 2-32
2.3.16 Processor Identification Register (PIR)..................................................................... 2-32
2.3.17 Synchronization Requirements for Special Registers and for Lookaside Buffers..... 2-33
Chapter 3
Operand Conventions
3.1 Data Organization in Memory and Data Transfers..........................................................3-1
3.1.1 Aligned and Misaligned Accesses............................................................................... 3-1
3.1.2 Byte Ordering ..............................................................................................................3-2
3.1.3 Structure Mapping Examples....................................................................................... 3-2
3.1.3.1 Big-Endian Mapping ............................................................................................... 3-2
3.1.3.2 Little-Endian Mapping.............................................................................................3-3
3.1.4 Byte Ordering in PowerPC Architecture ..................................................................... 3-4
3.1.4.1 Aligned Scalars in Little-Endian Mode................................................................... 3-4
3.1.4.2 Misaligned Scalars in Little-Endian Mode.............................................................. 3-6
3.1.4.3 Nonscalars................................................................................................................3-7
3.1.4.4 Instruction Addressing in Little-Endian Mode........................................................ 3-7
3.1.4.5 Input/Output Data Transfer Addressing in Little-Endian Mode..............................3-8
3.2 Operand Placement and Performance—VEA.................................................................. 3-8
3.2.1 Summary of Performance Effects................................................................................ 3-8
3.2.2 Instruction Restart...................................................................................................... 3-10
3.3 Floating-Point Execution Models—UISA..................................................................... 3-10
3.3.1 Floating-Point Data Format ....................................................................................... 3-11
3.3.1.1 Value Representation ............................................................................................. 3-12
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