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MPC8349EVVAJDB 产品描述及参数 - NXP（恩智浦）
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NXP（恩智浦）
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微处理器
封装:
TBGA-672
描述:
微处理器 - MPU 8349 TBGA NO PB W/ ENC
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MPC8349EVVAJDB数据手册
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Freescale Semiconductor
Application Note
© Freescale Semiconductor, Inc., 1999, 2006. All rights reserved.
This document describes the instruction and data cache
locking features on the e300 processor core, an
MPC603E-based core used in the MPC8349E integrated
microprocessor. Table 1 shows the cache characteristics of
the e300 processor core.
1 Cache Locking Terminology
In this document, a cache is either an instruction or data
cache unless otherwise specified. Cache locking is the ability
to prevent overwriting of some or all of a microprocessor
instruction or data cache. Cache locking can occur for either
an entire cache or for individual ways within the cache.
When an entire cache is locked, hits within the cache are
supplied in the same manner as hits to an unlocked cache.
Any access that misses in the cache is treated as a
cache-inhibited access. Cache entries that are invalid at the
time of locking remain invalid and inaccessible until the
Table 1. e300 Processor Core Cache Organization
Instruction
Cache Size
Data Cache
Size
Associativity Block Size Way Size
32 Kbytes 32 Kbytes 8 ways 8 words 4 Kbytes
Document Number: AN2129
Rev. 1, 07/2006
Contents
1 Cache Locking Terminology . . . . . . . . . . . . . . . . . . . .1
2 Overview of Cache Locking on the e300 Processor . . .2
3 Set Up Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
4 Disable Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5 Invalidate the Caches . . . . . . . . . . . . . . . . . . . . . . . . . .4
5.1 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . .4
5.2 Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
6 Load the Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
6.1 Preload Instructions into the Instruction Cache . . .6
6.2 Load Data into the Data Cache . . . . . . . . . . . . . . . .7
7 Lock the Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
7.1 Lock the Entire Instruction Cache . . . . . . . . . . . . .7
7.2 Instruction Cache Way Locking . . . . . . . . . . . . . . .7
7.3 Lock the Entire Data Cache 8
7.4 Data Cache Way Locking . . . . . . . . . . . . . . . . . . . .8
7.5 Invalidate a Locked Cache. . . . . . . . . . . . . . . . . . . 9
7.6 Cache Locking Register Summary . . . . . . . . . . . . .9
8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Instruction and Data Cache Locking
on the e300 Processor Core
by Jim Robertson and Kalpesh Gala
NCSG Applications
Freescale Semiconductor, Inc.
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