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MT48LC4M32B2P-6A:L
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MT48LC4M32B2P-6A:L数据手册
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SDR SDRAM
MT48LC4M32B2 – 1 Meg x 32 x 4 Banks
Features
PC100-compliant
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto precharge, includes concurrent auto precharge
and auto refresh modes
Self refresh mode (not available on AT devices)
Auto refresh
64ms, 4096-cycle refresh (commercial and
industrial)
16ms, 4096-cycle refresh (automotive)
LVTTL-compatible inputs and outputs
Single 3.3V ±0.3V power supply
Supports CAS latency (CL) of 1, 2, and 3
Options Marking
Configuration
4 Meg x 32 (1 Meg x 32 x 4 banks) 4M32B2
Package – OCPL
1
86-pin TSOP II (400 mil) TG
86-pin TSOP II (400 mil) Pb-free P
90-ball VFBGA (8mm x 13mm) F5
90-ball VFBGA (8mm x 13mm) Pb-
free
B5
Timing (cycle time)
6ns (167 MHz) -6A
2
6ns (167 MHz) -6
3
7ns (143 MHz) -7
3
Revision :G/:L
Operating temperature range
Commercial (0°C to +70°C) None
Industrial (–40°C to +85°C) IT
Automotive (–40°C to +105°C) AT
4
Notes:
1. Off-center parting line.
2. Available only on Revision L.
3. Available only on Revision G.
4. Contact Micron for availability.
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
Clock
Frequency (MHz)
Target
t
RCD-
t
RP-CL
t
RCD (ns)
t
RP (ns) CL (ns)
-6A 167 3-3-3 18 18 18
-6 167 3-3-3 18 18 18
-7 143 3-3-3 20 20 21
128Mb: x32 SDRAM
Features
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. V 03/16 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2001 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

MT48LC4M32B2P-6A:L 数据手册

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