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Empirical Evaluation of NAND Flash Memory Performance
Peter Desnoyers
Northeastern University
360 Huntington Ave.
Boston, MA 02115
pjd@ccs.neu.edu
ABSTRACT
Reports of NAND flash device testing in the literature have
for the most part been limited to examination of circuit-level
parameters on raw flash chips or prototypes, and system-
level parameters on entire storage subsystems. However,
there has been little examination of system-level parameters
of raw devices, such as mean latency and endurance values.
We report the results of such tests on a variety of devices.
Read, program, and erase latency were found to align closely
with manufacturer’s specified “typical” values in almost all
cases. Program/erase endurance, however, was found to ex-
ceed specified minimum values, often by as much as a factor
of 100. In addition significant performance changes were
found with wear. These changes may be used to track wear,
and in addition have significant implications for system per-
formance over the lifespan of a device. Finally, random write
patterns which incur performance penalties on current flash-
based memory systems were found to incur no overhead on
the devices themselves.
1. INTRODUCTION
Fixed magnetic disk has been the predominant media for
secondary storage for over three decades. In the last five
years, however, solid state storage in the form of NAND
flash memory has come into increasing use, becoming the
first competitor to magnetic disk storage to gain significant
commercial acceptance.
With the increasing use of flash-based secondary storage,
detailed understanding of behavior which affects operating
system design and performance becomes important. How-
ever, while disk behavior has been extensively studied, there
appear to be few sources for the information needed to pre-
dict performance and reliability of flash-based storage sys-
tems. Detailed studies of low-level electrical characteristics
are available [5, 6, 10], as well as performance studies of
complete storage assemblies (e.g. SSDs) containing flash
chips and controllers [1, 9]. However, to the best of our
knowledge, there is no experimental study to date of actual
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flash chips giving measured values for read, write, and erase
speed, power consumption, or write/erase longevity.
This paper reports measurements of these parameters for
a range of raw flash chips. We focus on chips themselves,
rather than flash-based systems such as USB drives or SSDs,
in order to better understand the capabilities and limitations
of the underlying technology.
Of the results found, the most unexpected were these:
• High program/erase endurance. Although NAND flash
memory degrades with repeated program/erase cycles, mea-
sured lifetime varies greatly, and is often as much as 100×
higher than manufacturer specifications.
• Wear-dependent performance changes. On all chips
tested, repeated program/erase cycling of a single block
decreases write time and increases erase time—by as much
as a factor of three or more—as that block wears out. This
changes overall system performance, as well as providing
a predictor of individual block failure.
• Random program speed. Flash-based storage systems
such as SSDs often have poor random write performance
[1], but this is not an attribute of the technology itself. In
our testing, non-sequential writes were found to perform
as well as sequential ones.
In the remainder of this paper we first present an overview
of flash memory technology from a system perspective in
Section 2, followed by experimental results (Section 3) and
conclusions (Section 4).
2. BACKGROUND
NAND flash is a form of electrically erasable pro-
grammable read-only memory based on a particularly space-
efficient basic cell, optimized for mass storage applications.
Unlike most memory technologies, NAND flash is organized
in pages of typically 2K or 4K bytes which are read and
written as a unit. Unlike block-oriented disk drives, how-
ever, pages must be erased in units of erase blocks com-
prising multiple pages—typically 32 to 128—before being
re-written.
2.1 Technical Overview
To inform our discussion we present an overview of the
circuit and electrical aspects of flash technology which are
relevant to system software performance; a deeper discussion
of these and other issues may be found in the survey by
Sanvido et al [11].
Cell architecture: The basic cell in a NAND flash is
a MOSFET transistor with a floating (i.e. oxide-isolated)
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