Datasheet 搜索 > 微处理器 > NXP（恩智浦） > P1013NXN2HFB 数据手册 > P1013NXN2HFB 产品描述及参数 1/95 页
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P1013NXN2HFB 产品描述及参数 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微处理器
封装:
BGA-689
描述:
PowerPC系列 1.055GHz
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P4P5P6P7P8P9P10P11P12P13P14P15Hot
典型应用电路图在P77
原理图在P3P33
封装尺寸在P92P93
型号编码规则在P93
标记信息在P93
技术参数、封装参数在P1P3P4P5P6P7P8P9P10P11P12P13
电气规格在P23P24P25P26P27P28P29P30P31P32P33P34
型号编号列表在P93
导航目录
P1013NXN2HFB数据手册
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WB-TePBGA II—689
31 mm x 31 mm
Freescale Semiconductor
Data Sheet: Technical Data
© 2011 Freescale Semiconductor, Inc. All rights reserved.
The following list provides an overview of the P1013 feature
set:
• One high-performance 32-bit e500v2 core that implements
the Power Architecture® technology:
• 36-bit physical addressing
– Double-precision floating-point support
– 32-Kbyte L1 instruction cache and 32-Kbyte L1 data
cache for each core
– 400-MHz to 1067-MHz clock frequency
• 256-Kbyte L2 cache with ECC. Also configurable as
SRAM and stashing memory.
• e500 coherency module (ECM) manages core and
intrasystem transactions
• Integrated security engine (SEC)
– Protocol support includes ARC4, 3DES, AES,
RSA/ECC, RNG, single-pass SSL/TLS
– XOR acceleration
• 64-bit DDR2/DDR3 SDRAM memory controller with
ECC support
– 32/64 bit data interface
– DDR2/3 supported for data rate up to 667 MHz
– Four banks of memory supported, each up to 8 Gbytes
• Programmable interrupt controller (PIC) compliant with
OpenPIC standard
• Dual I
2
C controllers
• Enhanced secure digital host controller (SD/MMC)
• Enhanced Serial peripheral interface (eSPI)
• Enhanced local bus controller (eLBC)
• Display interface unit (DIU)
• I2S interface supported through synchronous serial
interface (SSI)
• DUART
• Two High-Speed USB controller (USB 2.0)
– Host and device support
– Enhanced host controller interface (EHCI)
– ULPI interface to PHY
• Two enhanced three-speed Ethernet controllers (eTSECs)
– TCP/IP acceleration, quality of service, and
classification capabilities
– IEEE Std 1588™ support
– Lossless flow control
– RGMII, RMII, SGMII
• Two four-channel DMA controllers
• 87 general-purpose I/O signals
• Three PCI Express controllers
• Dual serial ATA (SATA) controllers
• TDM Interface
• Power management
• System performance monitor
• System access port
• IEEE Std 1149.1™- compatible, JTAG boundary scan
• Operating junction temperature (T
j
) range: 0–105C and
–40–125C (industrial specification)
• 31 31 mm 689-pin WB-TePBGA II (wire bond
temperature-enhanced plastic BGA)
P1013 QorIQ Integrated
Processor Hardware
Specifications
Document Number: P1013EC
Rev. 0, 11/2011
P1013
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