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Datasheet 搜索 > 微控制器 > Microchip(微芯) > PIC16F1526T-I/PT 数据手册 > PIC16F1526T-I/PT 其他数据使用手册 5/9 页
PIC16F1526T-I/PT
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PIC16F1526T-I/PT数据手册
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2011-2014 Microchip Technology Inc. DS80000520E-page 5
PIC16(L)F1526/1527
5. Module: MSSP (Master Synchronous
Serial Port)
5.1 SPI Master mode
When the MSSP is used in SPI Master mode and
the CKE bit is clear (CKE = 0), the Buffer Full (BF)
bit and the MSSP Interrupt Flag (SSPIF) bit
becomes set half an SCK cycle early. If the user
software immediately reacts to either of the bits
being set, a write collision may occur as indicated
by the WCOL bit being set.
Work around
To avoid a write collision one of the following
methods should be used:
Method 1: Add a software delay of one SCK
period after detecting the
completed transfer (the BF bit or
SSPIF bit becomes set) and prior
to writing to the SSPBUF register.
Verify the WCOL bit is clear after
writing to SSPBUF. If the WCOL
bit is set, clear the bit in software
and rewrite the SSPBUF register.
Method 2: As part of the MSSP initialization
procedure, set the CKE bit
(CKE = 1).
Affected Silicon Revisions
A2 A3 A5
X X X

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