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PIC16F18313-E/P 其他数据使用手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
PDIP-8
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P4P11P12P13P14P15P154P285P374P375Hot
典型应用电路图在P163P375
原理图在P10P19P58P67P76P107P142P155P160P166P167P174
封装尺寸在P449
标记信息在P445P446P447P448
封装信息在P445P449P450P451P452P454P455P456P458P459P461P462
技术参数、封装参数在P70P87P104P105P167P168P224P398P403P404P406P408
应用领域在P56
电气规格在P87P104P105P224
导航目录
PIC16F18313-E/P数据手册
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2015-2019 Microchip Technology Inc. DS40001799F-page 1
PIC16(L)F18313/18323
Description
PIC16(L)F18313/18323 microcontrollers feature Analog, Core Independent Peripherals and Communication
Peripherals, combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications.
The Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP,
PWM and communications) to add flexibility to the application design.
Core Features
• C Compiler Optimized RISC Architecture
• Only 48 Instructions
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Up to Four 8-bit Timers
• Up to Three 16-bit Timers
• Low-Current Power-on Reset (POR)
• Power-up Timer (PWRT)
• Brown-out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Extended Watchdog Timer (WDT) with Dedicated
On-Chip Oscillator for Reliable Operation
• Programmable Code Protection
Memory
• 3.5 Kbytes Program Flash Memory
• 256B Data SRAM Memory
• 256B of EEPROM
• Direct, Indirect and Relative Addressing Modes
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF18313/18323)
- 2.3V to 5.5V (PIC16F18313/18323)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
eXtreme Low-Power (XLP) Features
• Sleep mode: 40 nA @ 1.8V, typical
• Watchdog Timer: 250 nA @ 1.8V, typical
• Secondary Oscillator: 300 nA @ 32 kHz
• Operating Current:
-8 A @ 32 kHz, 1.8V, typical
- 37 A/MHz @ 1.8V, typical
Power-Saving Functionality
• Idle mode: ability to put the CPU core to Sleep
while internal peripherals continue operating from
the system clock
• Doze mode: ability to run the CPU core slower
than the system clock used by the internal periph-
erals
• Sleep mode: Lowest Power Consumption
• Peripheral Module Disable (PMD): peripheral
power disable hardware module to minimize
power consumption of unused peripherals
Digital Peripherals
• Configurable Logic Cell (CLC):
-Two CLCs
- Integrated combinational and sequential logic
• Complementary Waveform Generator (CWG):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
• Capture/Compare/PWM (CCP) modules:
- Two CCPs
- 16-bit resolution for Capture/Compare modes
- 10-bit resolution for PWM mode
• Pulse-Width Modulators (PWM)
- Two 10-bit PWMs
• Numerically Controlled Oscillator (NCO):
- Precision linear frequency generator (@50%
duty cycle) with 0.0001% step size of source
input clock
- Input Clock: 0 Hz < F
NCO
< 32 MHz
- Resolution: F
NCO
/2
20
• Serial Communications:
- EUSART
- RS-232, RS-485, LIN compatible
- Auto-Baud Detect, auto-wake-up on start
- Master Synchronous Serial Port (MSSP)
- SPI
-I
2
C, SMBus, PMBus™ compatible
• Data Signal Modulator (DSM):
- Modulates a carrier signal with digital data to
create custom carrier synchronized output
waveforms
Full-Featured, Low Pin Count Microcontrollers with XLP
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