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PIC18F2331T-E/SOG 其他数据使用手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
SOIC-28
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PIC18F2331T-E/SOG数据手册
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© 2005 Microchip Technology Inc. DS80180C-page 3
PIC18F2331/2431/4331/4431
10. Module: Program Memory
When writing to the program memory, the contents
of the program memory may not be written as
expected if the internal voltage reference is not
enabled.
Work around
Either of two workarounds can be used:
1. Before beginning any writes to the program
memory, enable the LVD (any voltage) and
wait for the internal voltage reference to
become stable. LVD interrupt requests may be
ignored. Once the LVD voltage reference is
stable, perform all program memory writes nor-
mally. When writes have been completed, the
LVD may be disabled.
2. Configure the BOR as enabled (any voltage).
Select a threshold below VDD to allow normal
operation. If V
DD is below the BOR threshold,
the device will be held in BOR Reset.
Date Codes that pertain to this issue:
All engineering and production devices.
11. Module: Core (DAW Instruction)
The DAW instruction may improperly clear the
Carry bit (Status<0>) when executed.
Work around
Test the Carry bit state before executing the DAW
instruction. If the Carry bit is set, increment the
next higher byte to be added, using an instruction
such as INCFSZ (this instruction does not affect
any Status flags and will not overflow a BCD
nibble). After the DAW instruction has been
executed, process the Carry bit normally (see
Example 1).
EXAMPLE 1: PROCESSING THE CARRY
BIT DURING BCD ADDITIONS
Date Codes that pertain to this issue:
All engineering and production devices.
12. Module: EUSART
Bit SENDB in the TXSTA register is not automati-
cally cleared by hardware upon completion of
transmission of a Sync Break.
Work around
Check the TRMT bit in TXSTA. If the TRMT bit is
set, Break transmission is said to be complete.
13. Module: EUSART
If the transmitter is left enabled while the module is
performing an auto-baud operation, an arbitrary
data byte may get transmitted.
Work around
Clear TXEN (TXSTA<5>) before any auto-baud
operation and set it after auto-baud is complete.
Enable TXEN only when a data byte is to be
transmitted. Care must be taken to ensure that the
TX pin is pulled high, either through an external
resistor, or by making the TX pin an output and
writing ‘1’ to it to not disturb the transmit line.
14. Module: EUSART
This module may perform incorrect auto-baud
calculation if the ABDEN (BAUDCON<0>) bit was
set while the receive pin was at a low level.
Work around
Wait for the RX pin to go high and then set the
ABDEN bit.
15. Module: EUSART
In Asynchronous Receiver mode, the EUSART
does not load the SPBRGH value after completion
of auto-baud.
Work around
Do not enable the BRG16 (BAUDCON<3>) bit.
If the BRG16 is in use, ensure that the auto-baud
SPBRG value does not exceed the 8-bit value.
16. Module: EUSART
The CREN (RCSTA<4>) bit is cleared after every
auto-baud operation.
Work around
Upon completion of auto-baud, manually set the
CREN bit.
MOVLW 0x80 ; .80 (BCD)
ADDLW 0x80 ; .80 (BCD)
BTFSC STATUS, C ; test C
INCFSZ byte2 ; inc next higher LSB
DAW
BTFSC STATUS, C ; test C
INCFSZ byte2 ; inc next higher LSB
This is repeated for each DAW instruction.
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